This documentation is automatically generated from source code on every push into master which pass testing. hwtLib is package of hardware components (like vhld/verilog library) for HWToolkit (hwt python3 module) it also contains most used helpers and types like uint64_t, UDP header etc. Library is structuralized mostly by main interface of component.
Interfaces of components are usually not shown in documentation directly instead they are declared in _declr() method of unit and they can be seen in sourcecode same for parameters in _config().
hwtLib.abstract.busEndpoint.
BusEndpoint
(structTemplate, intfCls=None, shouldEnterFn=None)[source]¶Bases: hwt.synthesizer.unit.Unit
Abstract unit Delegate request from bus to fields of structure (fields are represented by various interfaces) write has higher priority
__init__
(structTemplate, intfCls=None, shouldEnterFn=None)[source]¶Parameters: |
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_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_mkFieldInterface
(structIntf, field)[source]¶Instantiate field interface for fields in structure template of this endpoint
Returns: | interface for specified field |
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connectByInterfaceMap
(interfaceMap)[source]¶Connect “decoded” struct interface to interfaces specified in iterface map
Parameters: | interfaceMap – list of interfaces or tuple (type or interface, name) |
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fromInterfaceMap
(interfaceMap)[source]¶Generate converter by specified struct
Parameters: | interfaceMap – take a look at HTypeFromIntfMap if interface is specified it will be automatically connected |
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propagateAddr
(srcAddrSig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, srcAddrStep: int, dstAddrSig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, dstAddrStep: int, transTmpl: hwt.hdl.transTmpl.TransTmpl)[source]¶Parameters: |
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hwtLib.abstract.denseMemory.
AllocationError
[source]¶Bases: Exception
Exception which says that requested allocation can not be performed
hwtLib.abstract.denseMemory.
DenseMemory
(cellWidth, clk, rDatapumpIntf=None, wDatapumpIntf=None, parent=None)[source]¶Bases: object
Dense memory for simulation purposes with datapump interfaces
Variables: | data – memory dict |
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__init__
(cellWidth, clk, rDatapumpIntf=None, wDatapumpIntf=None, parent=None)[source]¶Parameters: |
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_getStruct
(offset, transTmpl)[source]¶Parameters: |
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calloc
(num, size, keepOut=None, initValues=None)[source]¶Allocates a block of memory for an array of num elements, each of them size bytes long, and initializes all its bits to zero.
Parameters: |
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Returns: | address of allocated memory |
getBits
(start, end)[source]¶Gets value of bits between selected range from memory
Parameters: |
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Returns: | instance of BitsVal (derived from SimBits type) which contains copy of selected bits |
getStruct
(addr, structT, bitAddr=None)[source]¶Get HStruct from memory
Parameters: |
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hwtLib.abstract.denseMemory.
reshapedInitItems
(actualCellSize, requestedCellSize, values)[source]¶Convert array item size and items cnt while size of array remains unchanged
Parameters: |
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Returns: | generator of new items of specified characteristik |
hwtLib.abstract.discoverAddressSpace.
AddressSpaceProbe
(topIntf, getMainSigFn, offset=0)[source]¶Bases: object
hwtLib.abstract.streamBuilder.
AbstractStreamBuilder
(parent, srcInterface, name=None)[source]¶Bases: object
Attention: | this is just abstract class unit classes has to be specified in concrete implementation |
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Variables: |
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Attention: | input port is taken from self.end |
FifoCls
= NotImplemented¶JoinFairCls
= NotImplemented¶JoinPrioritizedCls
= NotImplemented¶JoinSelectCls
= NotImplemented¶RegCls
= NotImplemented¶ResizerCls
= NotImplemented¶SplitCopyCls
= NotImplemented¶SplitFairCls
= NotImplemented¶SplitPrioritizedCls
= NotImplemented¶SplitSelectCls
= NotImplemented¶__init__
(parent, srcInterface, name=None)[source]¶Parameters: |
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_genericInstance
(unitCls, unitName, setParams=<function AbstractStreamBuilder.<lambda>>)[source]¶Instantiate generic component and connect basics
Parameters: |
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_join
(joinCls, parent, srcInterfaces, name, configAs, extraConfigFn)[source]¶Create builder from many interfaces by joining them together
Parameters: |
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buff
(items=1, latency=None, delay=None)[source]¶Use registers and fifos to create buffer of specified paramters :note: if items <= latency registers are used else fifo is used
Parameters: |
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Note: | delay can be used as synchronization method or to solve timing related problems because it will split valid signal path |
Note: | if latency or delay is None the most optimal value is used |
join_fair
(parent, srcInterfaces, name=None, configAs=None, exportSelected=False)[source]¶create builder from fairly joined interfaces (round robin for input select)
Parameters: | exportSelected – if True join component will have handshaked interface with index of selected input |
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Note: | other parameters same as in .AbstractStreamBuilder.join_fair |
split_copy
(noOfOutputs)[source]¶Clone input data to all outputs
Parameters: | noOfOutputs – number of output interfaces of the split |
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split_copy_to
(*outputs)[source]¶Same like split_copy, but outputs are automatically connected
Parameters: | outputs – ports on which should be outputs of split component connected to |
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split_fair
(noOfOutputs, exportSelected=False)[source]¶Create a rund robin selector with number of outputs specified by noOfOutputs
Parameters: |
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split_fair_to
(*outputs, exportSelected=False)[source]¶Same like split_fair, but outputs are automatically connected
Parameters: |
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split_prioritized
(noOfOutputs)[source]¶data from input is send to output witch is ready and has highest priority from all ready outputs
Parameters: | noOfOutputs – number of output interfaces of the fork |
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split_prioritized_to
(*outputs)[source]¶Same like split_prioritized, but outputs are automatically connected
Parameters: | outputs – ports on which should be outputs of split component connected to |
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split_select
(outputSelSignalOrSequence, noOfOutputs)[source]¶Create a demultiplexer with number of outputs specified by noOfOutputs
Parameters: |
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hwtLib.amba.axiLite_comp.endpoint.
AxiLiteEndpoint
(structTemplate, intfCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, shouldEnterFn=None)[source]¶Bases: hwtLib.abstract.busEndpoint.BusEndpoint
Delegate request from AxiLite interface to fields of structure write has higher priority
__init__
(structTemplate, intfCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, shouldEnterFn=None)[source]¶Parameters: |
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_getAddrStep
()¶Returns: | how many bits is one unit of address (f.e. 8 bits for char * pointer, 36 for 36 bit bram) |
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_getWordAddrStep
()¶Returns: | size of one word in unit of address |
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hwtLib.amba.axiLite_comp.reg.
AxiLiteReg
(axiCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]¶Bases: hwt.synthesizer.unit.Unit
Register for AXI3/4/lite interface
__init__
(axiCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.axi_comp.tester.
AxiTester
(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]¶Bases: hwt.synthesizer.unit.Unit
Tester for AXI3/4 interfaces
Can precisely control order and timing of read address/write address/read/write/write response transactions Allows to read and specify values of controls signals like cache/lock/burst etc…
__init__
(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.axi_comp.transCounter.
AxiTransactionCouter
(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶Bases: hwt.synthesizer.unit.Unit
Counter of beats on axi interface write to control register to clear counters
__init__
(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.base.
AxiSCompBase
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Abstract base for axis components
hwtLib.amba.axis_comp.builder.
AxiSBuilder
(parent, srcInterface, name=None)[source]¶Bases: hwtLib.abstract.streamBuilder.AbstractStreamBuilder
Helper class which simplifies building of large stream paths
Variables: | end – actual endpoint where building process will continue |
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FifoCls
¶alias of hwtLib.amba.axis_comp.fifo.AxiSFifo
RegCls
¶alias of hwtLib.amba.axis_comp.reg.AxiSReg
ResizerCls
¶SplitCopyCls
¶SplitSelectCls
¶forge
(parent, typeToForge, intfCls, setupFn=None, name=None)[source]¶generate frame assembler for specified type :note: you can set endianity and others in setupFn
Parameters: |
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Returns: | tuple (builder, interface with forged frame) |
hwtLib.amba.axis_comp.en.
AxiS_en
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
This component is like on-off switch for axi stream interface which does care about frames. If en signal is 0 current frame is finished and next frame is started only when en is 1
hwtLib.amba.axis_comp.fifo.
AxiSFifo
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.handshaked.fifo.HandshakedFifo
Synchronous fifo for axi-stream interface.
_regCls
¶alias of hwtLib.amba.axis_comp.reg.AxiSReg
hwtLib.amba.axis_comp.frameForge.
AxiS_frameForge
(axiSIntfCls, structT: hwt.hdl.types.hdlType.HdlType, tmpl: Union[hwt.hdl.transTmpl.TransTmpl, NoneType] = None, frames: Union[List[hwt.hdl.frameTmpl.FrameTmpl], NoneType] = None)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.amba.axis_comp.templateBasedUnit.TemplateBasedUnit
Assemble fields into frame on axi stream interface
Note: | names in the picture are just illustrative |
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__init__
(axiSIntfCls, structT: hwt.hdl.types.hdlType.HdlType, tmpl: Union[hwt.hdl.transTmpl.TransTmpl, NoneType] = None, frames: Union[List[hwt.hdl.frameTmpl.FrameTmpl], NoneType] = None)[source]¶Parameters: |
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Note: | if tmpl and frames are None they are resolved from structT parseTemplate |
Note: | this unit can parse sequence of frames, if they are specified by “frames” |
Note: | structT can contain fields with variable size like HStream |
_mkFieldIntf
(parent: hwt.interfaces.structIntf.StructIntf, structField: hwt.hdl.types.struct.HStructField)[source]¶Instantiate interface for all members of input type
connectPartsOfWord
(wordData_out: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, tPart: Union[hwt.hdl.transPart.TransPart, hwt.hdl.frameTmplUtils.ChoicesOfFrameParts], inPorts_out: List[Union[hwt.interfaces.std.Handshaked, hwtLib.handshaked.streamNode.StreamNode]], lastInPorts_out: List[Union[hwt.interfaces.std.Handshaked, hwtLib.handshaked.streamNode.StreamNode]])[source]¶Connect transactions parts to signal for word of output stream
Parameters: |
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hwtLib.amba.axis_comp.frameGen.
AxisFrameGen
[source]¶Bases: hwt.synthesizer.unit.Unit
Generator of axi stream frames for testing purposes
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.frameLinkConv.
AxiSToFrameLink
[source]¶Bases: hwt.synthesizer.unit.Unit
Axi 4 stream to FrameLink
format of user signal: user[0]: start of packet user[1]: end of packet
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.frameLinkConv.
FrameLinkToAxiS
[source]¶Bases: hwt.synthesizer.unit.Unit
Framelink to axi-stream
format of user signal: user[0]: start of packet user[1]: end of packet
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.frameParser.
AxiS_frameParser
(axiSCls, structT: hwt.hdl.types.hdlType.HdlType, tmpl: Union[hwt.hdl.transTmpl.TransTmpl, NoneType] = None, frames: Union[List[hwt.hdl.frameTmpl.FrameTmpl], NoneType] = None)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.amba.axis_comp.templateBasedUnit.TemplateBasedUnit
Parse frame specified by HStruct into fields
Note: | names in the picture are just illustrative |
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__init__
(axiSCls, structT: hwt.hdl.types.hdlType.HdlType, tmpl: Union[hwt.hdl.transTmpl.TransTmpl, NoneType] = None, frames: Union[List[hwt.hdl.frameTmpl.FrameTmpl], NoneType] = None)[source]¶Parameters: |
|
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Note: | if tmpl and frames are None they are resolved from structT parseTemplate |
Note: | this unit can parse sequence of frames, if they are specified by “frames” |
Attention: | structT can not contain fields with variable size like HStream |
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_mkFieldIntf
(parent: hwt.interfaces.structIntf.StructIntf, structField: hwt.hdl.types.struct.HStructField)[source]¶choiceIsSelected
(interfaceOfChoice: hwt.interfaces.unionIntf.UnionSink)[source]¶Check if union member is selected by _select interface in union interface
connectPart
(hsNondes: list, part: Union[hwt.hdl.transPart.TransPart, hwt.hdl.frameTmplUtils.ChoicesOfFrameParts], en: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, bool], exclusiveEn: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType] = <BitsVal 1, mask 1>)[source]¶Create datamux for one word in main fsm and colect metainformations for handshake logic
Parameters: | hsNondes – list of nodes of handshaked logic |
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hwtLib.amba.axis_comp.frameParser_utils.
ExclusieveListOfHsNodes
(selectorIntf)[source]¶Bases: list
@ivar selectorIntf: selector for this node
hwtLib.amba.axis_comp.frameParser_utils.
InNodeInfo
(inInterface: hwt.interfaces.std.Handshaked, en: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)[source]¶Bases: object
Interface has to be ready and handshaked logic should be constructed
hwtLib.amba.axis_comp.frameParser_utils.
InNodeReadOnlyInfo
(inInterface: hwt.interfaces.std.Handshaked, en: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)[source]¶Bases: hwtLib.amba.axis_comp.frameParser_utils.InNodeInfo
Interface has to be ready but handshake logic is not constructed
hwtLib.amba.axis_comp.frameParser_utils.
OutNodeInfo
(parent: hwt.synthesizer.unit.Unit, outInterface: hwt.interfaces.std.VldSynced, en: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, exclusiveEn: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType] = None)[source]¶Bases: object
Container for informations about output for handshake logic
Variables: |
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hwtLib.amba.axis_comp.frameParser_utils.
WordFactory
(wordIndexReg: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType])[source]¶Bases: object
hwtLib.amba.axis_comp.measuringFifo.
AxiS_measuringFifo
(stream_t=<class 'hwtLib.amba.axis.AxiStream'>)[source]¶Bases: hwt.synthesizer.unit.Unit
Fifo which are counting sizes of frames and sends it over dedicated handshaked interface “sizes”
__init__
(stream_t=<class 'hwtLib.amba.axis.AxiStream'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.reg.
AxiSReg
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.handshaked.reg.HandshakedReg
Register for axi stream interface
hwtLib.amba.axis_comp.resizer.
AxiS_resizer
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
Change data with of interface
Attention: | start of frame is expected to be aligned on first word |
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Attention: | strb can be not fully set only in last word |
Attention: | in upscale mode id and other signals which are not dependent on data width are propagated only from last word |
_config
()[source]¶Configure object parameters
hwtLib.amba.axis_comp.splitCopy.
AxiSSplitCopy
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.handshaked.splitCopy.HsSplitCopy
hwtLib.amba.axis_comp.splitSelect.
AxiSSpliSelect
(hsIntfCls)[source]¶Bases: hwtLib.amba.axis_comp.base.AxiSCompBase
, hwtLib.handshaked.splitSelect.HsSplitSelect
hwtLib.amba.axis_comp.storedBurst.
AxiSStoredBurst
(data=[72, 101, 108, 108, 111, 32, 119, 111, 114, 108, 100])[source]¶Bases: hwt.synthesizer.unit.Unit
This units send data stored in property DATA over axi-stream interface
__init__
(data=[72, 101, 108, 108, 111, 32, 119, 111, 114, 108, 100])[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.interconnect.rStricOrder.
RStrictOrderInterconnect
[source]¶Bases: hwtLib.amba.interconnect.axiInterconnectbase.AxiInterconnectBase
Strict order interconnect for AxiRDatapumpIntf ensures that response on request is delivered to driver which asked for it while transactions can overlap
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
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Returns: | tuple (do serialize this object, next priv) |
hwtLib.amba.interconnect.wStrictOrder.
WStrictOrderInterconnect
[source]¶Bases: hwtLib.amba.interconnect.axiInterconnectbase.AxiInterconnectBase
Strict order interconnect for AxiWDatapumpIntf ensures that response on request is delivered to driver which asked for it while transactions can overlap
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
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Returns: | tuple (do serialize this object, next priv) |
hwtLib.amba.sim.axi3DenseMem.
Axi3DenseMem
(clk, axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None)[source]¶Bases: hwtLib.abstract.denseMemory.DenseMemory
Simulation memory for Axi3/4 interfaces (slave component)
__init__
(clk, axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None)[source]¶Parameters: |
|
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Attention: | use axi or axi parts not bouth |
Attention: | memories are commiting into memory in “data” property after transaction is complete |
hwtLib.amba.sim.axiMemSpaceMaster.
AxiLiteMemSpaceMaster
(bus, registerMap)[source]¶Bases: hwtLib.sim.abstractMemSpaceMaster.AbstractMemSpaceMaster
Controller of AxiLite simulation agent which keeps track of axi lite transactions and aggregates them to proper register names on target bus
_axi3lite_writeAddr
(addrChannel, addr, size)[source]¶add address transaction to addr channel of agent
_axi4lite_writeAddr
(addrChannel, addr, size)[source]¶add address transaction to addr channel of agent
hwtLib.amba.axi3.
Axi3
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite
Axi3 bus interface
LEN_WIDTH
= 4¶LOCK_WIDTH
= 2¶_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
Axi3_addr
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite_addr
, hwtLib.amba.axi_intf_common.Axi_id
Axi3 address channel interface
LEN_WIDTH
= 4¶LOCK_WIDTH
= 2¶_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
Axi3_addr_withUser
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3_addr
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
Axi3_addr_withUserAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for Axi3_addr_withUser
interface
input/output data stored in list under “data” property data contains tuples (id, addr, burst, cache, len, lock, prot, size, qos, user)
hwtLib.amba.axi3.
Axi3_b
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite_b
, hwtLib.amba.axi_intf_common.Axi_id
Axi3 write response channel interface
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
Axi3_bAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for Axi3_b
interface
input/output data stored in list under “data” property data contains tuples (id, resp)
hwtLib.amba.axi3.
Axi3_r
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite_r
, hwtLib.amba.axi_intf_common.Axi_id
Axi 3 read channel interface
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
Axi3_rAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for Axi4_r
interface
input/output data stored in list under “data” property data contains tuples (id, data, resp, last)
hwtLib.amba.axi3.
Axi3_w
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axis.AxiStream_withId
Axi3 write channel interface
hwtLib.amba.axi3.
Axi3_withAddrUser
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3
Axi3 bus interface with user signals on address channels
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3.
IP_Axi3
[source]¶Bases: hwtLib.amba.axi3Lite.IP_Axi3Lite
IP core interface meta for Axi3 interface
hwtLib.amba.axi3Lite.
Axi3Lite
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
hwtLib.amba.axi3Lite.
Axi3LiteAgent
(intf)[source]¶Bases: hwt.simulator.agentBase.AgentBase
Composite simulation agent with agent for every axi channel change of enable is propagated to each child
data for each agent is stored in agent for given channel (ar, aw, r, … property)
hwtLib.amba.axi3Lite.
Axi3Lite_addr
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi_intf_common.Axi_hs
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3Lite.
Axi3Lite_addrAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Variables: | data – iterable of addr |
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hwtLib.amba.axi3Lite.
Axi3Lite_b
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.amba.axi3Lite.
Axi3Lite_bAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Variables: | data – iterable of resp |
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hwtLib.amba.axi3Lite.
Axi3Lite_r
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi_intf_common.Axi_hs
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3Lite.
Axi3Lite_w
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi_intf_common.Axi_hs
_config
()[source]¶Configure object parameters
hwtLib.amba.axi3Lite.
Axi3Lite_wAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Variables: | data – iterable of tuples (data, strb) |
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hwtLib.amba.axi3Lite.
AxiLite_rAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Variables: | data – iterable of tuples (data, resp) |
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hwtLib.amba.axi3Lite.
IP_Axi3Lite
[source]¶Bases: hwt.serializer.ip_packager.interfaces.intfConfig.IntfConfig
asQuartusTcl
(buff: List[str], version: str, component, entity: hwt.hdl.entity.Entity, allInterfaces: List[hwt.synthesizer.interface.Interface], thisIf: hwt.synthesizer.interface.Interface)[source]¶Add interface to Quartus tcl
Parameters: |
|
---|
hwtLib.amba.axi4.
Axi4
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3
Basic AMBA AXI4 bus interface
Variables: |
|
---|
LEN_WIDTH
= 8¶LOCK_WIDTH
= 1¶_config
()[source]¶Configure object parameters
hwtLib.amba.axi4.
Axi4_addr
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3_addr
Axi4 address channel interface (axi3 address channel with different size of len and lock signals and additional qos signal)
LEN_WIDTH
= 8¶LOCK_WIDTH
= 1¶hwtLib.amba.axi4.
Axi4_b
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3_b
Axi4 write response channel interface (same as axi3)
hwtLib.amba.axi4.
Axi4_r
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3.Axi3_r
Axi4 read channel interface (same as axi3)
hwtLib.amba.axi4.
Axi4_w
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axis.AxiStream
Axi4 write channel interface (Axi3_w without id signal)
hwtLib.amba.axi4.
IP_Axi4
[source]¶Bases: hwtLib.amba.axi3.IP_Axi3
IP core interface meta for Axi4 interface
hwtLib.amba.axi4Lite.
Axi4Lite
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite
Axi4-lite bus interface
hwtLib.amba.axi4Lite.
Axi4Lite_addr
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.amba.axi4Lite.
Axi4Lite_addrAgent
(intf)[source]¶Bases: hwtLib.amba.axi3Lite.Axi3Lite_addrAgent
Variables: | data – iterable of addr |
---|
hwtLib.amba.axi4Lite.
Axi4Lite_b
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.amba.axi4Lite.
Axi4Lite_r
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.amba.axi4Lite.
Axi4Lite_w
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.amba.axi4Lite.
IP_Axi4Lite
[source]¶Bases: hwtLib.amba.axi3Lite.IP_Axi3Lite
IP core meta description for Axi4-lite interface
hwtLib.amba.axi4_rDatapump.
Axi_rDatapump
(axiAddrCls=<class 'hwtLib.amba.axi4.Axi4_addr'>)[source]¶hwtLib.amba.axi4_rDatapump.
TransEndInfo
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
hwtLib.amba.axi4_streamToMem.
Axi4streamToMem
[source]¶Bases: hwt.synthesizer.unit.Unit
Most simple DMA for AXI4 interface.
0x0 control reg.
rw bit 0 - on/off (1 means on) r bit 1 - idle
0x4 baseAddr
Length of written data is specified by DATA_LEN. Input data is splited on smaller frames to fit MAX_BUTST_LEN.
If there is transaction pending idle flag is 0, if on/off is set to 0 in this state unit continues until all data are send and then stayes off. This could be use as synchronization with the software.
or unit is enabled and driver disables it only for the time of reading.
_config
()[source]¶Configure object parameters
hwtLib.amba.axi4_wDatapump.
Axi_wDatapump
(axiAddrCls=<class 'hwtLib.amba.axi4.Axi4_addr'>, axiWCls=<class 'hwtLib.amba.axi4.Axi4_w'>)[source]¶Bases: hwtLib.amba.axi_datapump_base.Axi_datapumpBase
__init__
(axiAddrCls=<class 'hwtLib.amba.axi4.Axi4_addr'>, axiWCls=<class 'hwtLib.amba.axi4.Axi4_w'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
hwtLib.amba.axi4_wDatapump.
BFifoIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.Handshaked
hwtLib.amba.axi4_wDatapump.
WFifoIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.Handshaked
hwtLib.amba.axiDatapumpIntf.
AddrSizeHs
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.Handshaked
_config
()[source]¶Configure object parameters
hwtLib.amba.axiDatapumpIntf.
AddrSizeHsAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
hwtLib.amba.axiDatapumpIntf.
AxiRDatapumpIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
Interface of read datapump driver
_config
()[source]¶Configure object parameters
hwtLib.amba.axiDatapumpIntf.
AxiRDatapumpIntfAgent
(intf)[source]¶Bases: hwt.simulator.agentBase.AgentBase
Composite agent with agent for every AxiRDatapumpIntf channel enable is shared
enable
¶hwtLib.amba.axiDatapumpIntf.
AxiWDatapumpIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
Interface of write datapump driver
_config
()[source]¶Configure object parameters
hwtLib.amba.axi_datapump_base.
Axi_datapumpBase
(axiAddrCls=<class 'hwtLib.amba.axi4.Axi4_addr'>)[source]¶Bases: hwt.synthesizer.unit.Unit
Variables: |
|
---|
__init__
(axiAddrCls=<class 'hwtLib.amba.axi4.Axi4_addr'>)[source]¶Initialize self. See help(type(self)) for accurate signature.
_config
()[source]¶Configure object parameters
hwtLib.amba.axi_datapump_utils.
connectDp
(parent, controller, datapump, axi, exclude=None)[source]¶Connect datapump with it’s controller(s) and axi
Parameters: |
|
---|
hwtLib.amba.axi_intf_common.
Axi_hs
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
AXI handshake interface with ready and valid signal (same as HandshakeSync just vld is valid and rd is ready) transaction happens when both ready and valid are high
Variables: |
|
---|
hwtLib.amba.axi_intf_common.
Axi_id
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.amba.axi_intf_common.
Axi_strb
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.amba.axi_intf_common.
Axi_user
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.amba.axis.
AxiStream
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axis.AxiStream_withoutSTRB
, hwtLib.amba.axi_intf_common.Axi_strb
AxiStream_withoutSTRB
with strb signal
Variables: | strb – byte strobe signal, has bit for each byte of data, data valid if corresponding bit ins strb signal is high |
---|
_config
()[source]¶Configure object parameters
hwtLib.amba.axis.
AxiStreamAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for AxiStream
interface
input/output data stored in list under “data” property data contains tuples (data, strb, last)
hwtLib.amba.axis.
AxiStream_withId
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi_intf_common.Axi_id
, hwtLib.amba.axis.AxiStream
AxiStream
with id signal
Variables: | id – id signal, usually identifies type or destination of frame |
---|
_config
()[source]¶Configure object parameters
hwtLib.amba.axis.
AxiStream_withIdAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for AxiStream_withId
interface
input/output data stored in list under “data” property data contains tuples (id, data, strb, last)
hwtLib.amba.axis.
AxiStream_withUserAndNoStrb
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axis.AxiStream_withoutSTRB
, hwtLib.amba.axi_intf_common.Axi_user
AxiStream_withoutSTRB
with user signal
Variables: | user – generic signal with user specified meaning |
---|
hwtLib.amba.axis.
AxiStream_withUserAndStrb
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axis.AxiStream
, hwtLib.amba.axi_intf_common.Axi_user
AxiStream
with user signal
Variables: | user – generic signal with user specified meaning |
---|
_config
()[source]¶Configure object parameters
hwtLib.amba.axis.
AxiStream_withUserAndStrbAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for AxiStream_withUserAndStrb
interface
input/output data stored in list under “data” property data contains tuples (data, strb, user, last)
hwtLib.amba.axis.
AxiStream_withoutSTRB
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.amba.axi_intf_common.Axi_hs
Bare AMBA AXI-stream interface
Variables: |
|
---|---|
Attention: | no checks are made for endianity, this is just information |
Note: | bigendian for interface means that items which are send through this interface has reversed byte endianity that means that most significant byte is is on lower address than les significant ones f.e. litle endian value 0x1a2b will be 0x2b1a but iterface itselelf is not reversed in any way |
_config
()[source]¶Configure object parameters
hwtLib.amba.axis.
AxiStream_withoutSTRBAgent
(intf)[source]¶Bases: hwtLib.amba.sim.agentCommon.BaseAxiAgent
Simulation agent for AxiStream_withoutSTRB
interface
input/output data stored in list under “data” property data contains tuples (data, strb, last)
hwtLib.amba.axis.
IP_AXIStream
[source]¶Bases: hwt.serializer.ip_packager.interfaces.intfConfig.IntfConfig
Class which specifies how to describe AxiStream interfaces in IP-core
hwtLib.amba.fullDuplexAxiStream.
FullDuplexAxiStream
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.clocking.clkBuilder.
ClkBuilder
(parent, srcInterface, name=None)[source]¶Bases: object
Variables: |
---|
__init__
(parent, srcInterface, name=None)[source]¶Parameters: |
|
---|
edgeDetector
(sig, rise=False, fall=False, last=None, initVal=0)[source]¶Parameters: |
|
---|---|
Returns: | signals which is high on on rising/falling edge or both (specified by rise, fall parameter) |
oversample
(sig, sampleCount, sampleTick, rstSig=None) → Tuple[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal][source]¶[TODO] last sample is not sampled correctly
Parameters: |
|
---|---|
Returns: | typle (oversampled signal, oversample valid signal) |
timerDynamic
(periodSig, enableSig=None, rstSig=None) → hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]¶Same as timer, just period is signal which can be configured dynamically
timers
(periods, enableSig=None, rstSig=None)[source]¶generate counters specified by count of iterations
Parameters: |
|
---|---|
Attention: | if tick of timer his high and enableSig falls low tick will stay high |
Returns: | list of tick signals from timers |
hwtLib.clocking.clkDivider.
ClkDiv3
[source]¶Bases: hwt.synthesizer.unit.Unit
Attention: | this clock divider implementation suits well for generating of slow output clock inside fpga you should use clocking primitives (http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf) |
---|
hwtLib.clocking.timers.
DynamicTimerInfo
(maxVal, name=None)[source]¶Bases: hwtLib.clocking.timers.TimerInfo
Meta informations about timer with dynamic period
_instantiateTimerTickLogic
(timer: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, period: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, enableSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType], rstSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType])[source]¶Instantiate incrementing timer with optional reset and enable signal
Parameters: |
|
---|
hwtLib.clocking.timers.
TimerInfo
(maxVal, name=None)[source]¶Bases: object
Variables: |
|
---|
_instantiateTimer
(parentUnit, timer, enableSig=None, rstSig=None)[source]¶Parameters: |
|
---|
_instantiateTimerTickLogic
(parentUnit: hwt.synthesizer.unit.Unit, timer: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, origMaxVal: Union[int, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.hdl.value.Value], enableSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType], rstSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType]) → hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]¶Instantiate logic of this timer
Returns: | tick signal from this timer |
---|
cntrRegister
¶instantiate
(parentUnit, timers, enableSig=None, rstSig=None)[source]¶Parameters: |
|
---|
maxVal
¶maxValOriginal
¶name
¶parent
¶tick
¶hwtLib.handshaked.builder.
HsBuilder
(parent, srcInterface, name=None)[source]¶Bases: hwtLib.abstract.streamBuilder.AbstractStreamBuilder
Helper class which simplifies building of large stream paths
FifoCls
¶JoinExplicitCls
= NotImplemented¶JoinFairCls
¶JoinPrioritizedCls
¶alias of hwtLib.handshaked.joinPrioritized.HsJoinPrioritized
RegCls
¶alias of hwtLib.handshaked.reg.HandshakedReg
ResizerCls
¶alias of hwtLib.handshaked.resizer.HsResizer
SplitCopyCls
¶SplitFairCls
¶SplitPrioritizedCls
¶alias of hwtLib.handshaked.splitPrioritized.HsSplitPrioritized
SplitSelectCls
¶hwtLib.handshaked.compBase.
HandshakedCompBase
(hsIntfCls)[source]¶Bases: hwt.synthesizer.unit.Unit
__init__
(hsIntfCls)[source]¶Parameters: | hsIntfCls – class of interface which should be used as interface of this unit |
---|
hwtLib.handshaked.fifo.
HandshakedFifo
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Fifo for handshaked interfaces
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_regCls
¶alias of hwtLib.handshaked.reg.HandshakedReg
hwtLib.handshaked.intfBiDirectional.
HandshakedBiDirectional
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.Handshaked
hwt.interfaces.std.Handshaked
interface with datahwtLib.handshaked.intfBiDirectional.
HandshakedBiDirectionalAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
Simulation agent for HandshakedBiDirectional
interface
Attention: | for monitor number of items in dinData has to match with number of received items |
---|
Bases: hwtLib.handshaked.joinPrioritized.HsJoinPrioritized
Join input stream to single output stream inputs with lower number has higher priority
Priority is changing every clock If prioritized input is not sending valid data, input with lowest index and valid is used
combinational
Configure object parameters
declarations
implementations
Resolve isSelected signal flags for each input, when isSelected flag signal is 1 it means input has clearance to make transaction
Generate ack logic for selected input
Parameters: |
|
---|---|
Returns: | ack signal for this input |
hwtLib.handshaked.joinPrioritized.
HsJoinPrioritized
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Join input stream to single output stream inputs with lower number has higher priority
combinational
_config
()[source]¶Configure object parameters
hwtLib.handshaked.ramAsHs.
RamAsHs
[source]¶Bases: hwt.synthesizer.unit.Unit
Converter from ram port to handshaked interfaces
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.handshaked.ramAsHs.
RamHsR
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
_config
()[source]¶Configure object parameters
hwtLib.handshaked.reg.
HandshakedReg
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Register for Handshaked interface
_config
()[source]¶Configure object parameters
hwtLib.handshaked.resizer.
HsResizer
(hsIntfCls, scale, inIntfConfigFn, outIntfConfigFn)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Resize width of handshaked interface
__init__
(hsIntfCls, scale, inIntfConfigFn, outIntfConfigFn)[source]¶Parameters: |
|
---|
_config
()[source]¶Configure object parameters
hwtLib.handshaked.splitCopy.
HsSplitCopy
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Clone input stream to n identical output streams transaction is made in all interfaces or none of them
combinational
_config
()[source]¶Configure object parameters
hwtLib.handshaked.splitFair.
HsSplitFair
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.splitCopy.HsSplitCopy
Split input stream to outputs, select single output for every input data based on priority.
Priority is changing every clock If prioritized output is not ready, input with lowest index and ready is used
combinational
Variables: | selectedOneHot – handshaked interface with one hot encoded index of selected output |
---|
_config
()[source]¶Configure object parameters
hwtLib.handshaked.splitPrioritized.
HsSplitPrioritized
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.splitCopy.HsSplitCopy
Split input stream to n output streams Data is send to output interface which is ready and has lowest index
combinational
hwtLib.handshaked.splitSelect.
HsSplitSelect
(hsIntfCls)[source]¶Bases: hwtLib.handshaked.compBase.HandshakedCompBase
Split data from input interface to output interface based on explicit output index provided by select interface
_config
()[source]¶Configure object parameters
hwtLib.handshaked.streamNode.
ExclusiveStreamGroups
[source]¶Bases: list
list of tuples (cond, StreamNode instance) Only one stream from this group can be activated at the time
hwtLib.handshaked.streamNode.
StreamNode
(masters=None, slaves=None, extraConds=None, skipWhen=None)[source]¶Bases: object
Group of stream master and slave interfaces to synchronize them to each other
Variables: |
|
---|---|
Attention: | skipWhen has higher priority |
__init__
(masters=None, slaves=None, extraConds=None, skipWhen=None)[source]¶Initialize self. See help(type(self)) for accurate signature.
ack
()[source]¶Returns: | expression which’s value is high when transaction can be made over interfaces |
---|
hwtLib.i2c.intf.
I2c
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.i2c.intf.
I2cAgent
(intf, allowNoReset=True)[source]¶Bases: hwt.simulator.agentBase.AgentWitReset
START
= 'start'¶__init__
(intf, allowNoReset=True)[source]¶Initialize self. See help(type(self)) for accurate signature.
hwtLib.i2c.masterBitCntrl.
I2cBitCntrlCmd
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.RdSynced
_config
()[source]¶Configure object parameters
hwtLib.i2c.masterBitCntrl.
I2cBitCntrlCmdAgent
(intf, allowNoReset=True)[source]¶Bases: hwt.interfaces.agents.rdSynced.RdSyncedAgent
hwtLib.i2c.masterBitCntrl.
I2cMasterBitCtrl
[source]¶Bases: hwt.synthesizer.unit.Unit
Translate simple commands into SCL/SDA transitions Each command has 5 states, 0/1/2/3/idle
Timing: | Normal mode | Fast mode |
---|---|---|
Fscl | 100KHz | 400KHz |
Th_scl | 4.0us | 0.6us High period of SCL |
Tl_scl | 4.7us | 1.3us Low period of SCL |
Tsu:sta | 4.7us | 0.6us setup time for a repeated start condition |
Tsu:sto | 4.0us | 0.6us setup time for a stop condition |
Tbuf | 4.7us | 1.3us Bus free time between a stop and start condition |
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
hwtLib.interfaces.addrDataHs.
AddrDataBitMaskHs
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶hwtLib.interfaces.addrDataHs.
AddrDataHs
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
_config
()[source]¶Configure object parameters
hwtLib.interfaces.frameLink.
FrameLink
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
Stream with “byte enable” and “start/end of frame/packet”
hwtLib.ipif.endpoint.
IpifEndpoint
(structTemplate, intfCls=<class 'hwtLib.ipif.intf.Ipif'>, shouldEnterFn=None)[source]¶Bases: hwtLib.abstract.busEndpoint.BusEndpoint
Delegate request from bus to fields of structure
Attention: | interfaces are dynamically generated from names of fileds in structure template |
---|---|
Attention: | byte enable and register clock enable signals are ignored |
__init__
(structTemplate, intfCls=<class 'hwtLib.ipif.intf.Ipif'>, shouldEnterFn=None)[source]¶Parameters: |
|
---|
_getAddrStep
()¶Returns: | how many bits is one unit of address (f.e. 8 bits for char * pointer, 36 for 36 bit bram) |
---|
_getWordAddrStep
()¶Returns: | size of one word in unit of address |
---|
hwtLib.ipif.intf.
Ipif
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
READ
= 1¶WRITE
= 0¶_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
hwtLib.ipif.intf.
IpifAgent
(intf, allowNoReset=True)[source]¶Bases: hwt.simulator.agentBase.SyncAgentBase
Variables: |
|
---|
hwtLib.ipif.intf.
IpifWithCE
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.ipif.intf.Ipif
hwtLib.ipif.reg.
IpifReg
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.ipif.simMaster.
IPFISimMaster
(bus, registerMap)[source]¶Bases: hwtLib.sim.abstractMemSpaceMaster.AbstractMemSpaceMaster
Simulation address space master for IPIF interface
hwtLib.logic.binToOneHot.
BinToOneHot
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.logic.bitonicSorter.
BitonicSorter
(cmpFn=<function BitonicSorter.<lambda>>)[source]¶Bases: hwt.synthesizer.unit.Unit
__init__
(cmpFn=<function BitonicSorter.<lambda>>)[source]¶Parameters: | cmpFn – function (item0, item1) if returns true, items are not swaped |
---|
_config
()[source]¶Configure object parameters
hwtLib.logic.cntrGray.
GrayCntr
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.logic.crc.
Crc
[source]¶Bases: hwt.synthesizer.unit.Unit
Crc generator for any crc polynom can be string in usual format or integer f.e.”x^3+x+1” or 0b1011
_config
()[source]¶Configure object parameters
hwtLib.logic.crcComb.
CrcComb
[source]¶Bases: hwt.synthesizer.unit.Unit
CRC generator polynomial can be string in usual format or integer (f.e.”x^3+x+1” or 0b1011)
Attention: | Input not reflected, Result not reflected, Initial Value: 0x0, Final Xor is not applied |
---|---|
Variables: |
|
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
applyCrcXorMatrix
(crcMatrix: List, inBits: List, stateBits: List, refin: bool) → List[source]¶buildCrcXorMatrix
(data_width: int, polyBits: List[bool]) → List[Tuple[List[bool], List[bool]]][source]¶Parameters: | data_width – number of bits in input (excluding bits of signal wit current crc state) |
---|
:param polyBits :note: all bits are in format [LSB:MSB]
Returns: | crc_mask contains rows where each row describes which bits should be XORed to get bit of resut row is [mask_for_state_reg, mask_for_data] |
---|
hwtLib.logic.crcPoly.
CRC_1
[source]¶Bases: object
POLY
= 1¶REFIN
= False¶REFOUT
= False¶WIDTH
= 1¶hwtLib.logic.crcPoly.
CRC_16_CCITT
[source]¶Bases: object
INIT
= 65535¶POLY
= 4129¶REFIN
= False¶REFOUT
= False¶WIDTH
= 16¶XOROUT
= 0¶hwtLib.logic.crcPoly.
CRC_16_IBM
[source]¶Bases: object
INIT
= 0¶POLY
= 32773¶REFIN
= True¶REFOUT
= True¶WIDTH
= 16¶XOROUT
= 0¶hwtLib.logic.crcPoly.
CRC_32
[source]¶Bases: object
INIT
= 4294967295¶POLY
= 79764919¶REFIN
= True¶REFOUT
= True¶RESIDUE
= 3338984827¶WIDTH
= 32¶XOROUT
= 4294967295¶hwtLib.logic.crcPoly.
CRC_32C
[source]¶Bases: object
CHECK
= 3808858755¶INIT
= 4294967295¶POLY
= 517762881¶REFIN
= True¶REFOUT
= True¶RESIDUE
= 3080238136¶WIDTH
= 32¶XOROUT
= 4294967295¶hwtLib.logic.crcPoly.
CRC_3_GSM
[source]¶Bases: object
INIT
= 0¶POLY
= 3¶REFIN
= False¶REFOUT
= False¶WIDTH
= 3¶hwtLib.logic.crcPoly.
CRC_5_USB
[source]¶Bases: object
CHECK
= 25¶INIT
= 31¶POLY
= 5¶REFIN
= True¶REFOUT
= True¶RESIDUE
= 12¶WIDTH
= 5¶XOROUT
= 31¶hwtLib.logic.crcPoly.
CRC_64_ECMA
[source]¶Bases: object
POLY
= 4823603603198064275¶WIDTH
= 64¶hwtLib.logic.lsfr.
Lsfr
[source]¶Bases: hwt.synthesizer.unit.Unit
Linear shift feedback register, form of hardware pseudorandom generator
_config
()[source]¶Configure object parameters
hwtLib.logic.oneHotToBin.
OneHotToBin
[source]¶Bases: hwt.synthesizer.unit.Unit
Converts one hot signal to binary, bin.vld is high when oneHot != 0
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.logic.pid.
PidController
[source]¶Bases: hwt.synthesizer.unit.Unit
The PID Control block compares the input to the target and calculates an error. Based on this error, a output value is calculated that should result in a smaller error on the next iteration of the loop, assuming your parameters are tuned properly.
u(k) = u(k-1) + a0*e(k) + a1*y(k) + a2*y(k-1) + a3*y(k-2)
e(k): error in this step (= target value - input) y(k): input in step k ax: PID coeficient
The PID parameter inputs for this equation are slightly different from the traditional K_p, K_i, and K_d.
a0 = K_i * T_s a1 = -K_p - K_d / T_s a2 = K_p + 2K_d/T_s a3 = - K_d / T_s
Note: | You can obtain coeficiet f.e. by Ziegler-Nichols method. |
---|
_config
()[source]¶Configure object parameters
hwtLib.logic.segment7.
Segment7
[source]¶Bases: hwt.synthesizer.unit.Unit
7-segment display decoder
Note: | led in display becomes active when output = 0 |
---|
Display pin connection on image below.
-------------
| 0 |
-------------
| 5 | | 1 |
-------------
| 6 |
-------------
| 4 | | 2 |
-------------
| 3 |
-------------
hwtLib.mem.atomic.flipCntr.
FlipCntr
[source]¶Bases: hwt.synthesizer.unit.Unit
Counter with FlipRegister which is form memory with atomic access
interface doFilip drives switching of memories in flip register dataIn has higher priority than doIncr
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only first obj of it’s class
Parameters: | priv – private data for this function (first object with class == obj.__class__) |
---|---|
Returns: | tuple (do serialize this object, next priv) where priv is private data for this function (first object with class == obj.__class__) |
hwtLib.mem.atomic.flipRam.
FlipRam
[source]¶Bases: hwt.synthesizer.unit.Unit
Switchable RAM, there are two memories and two sets of ports, Each set of ports is every time connected to opposite ram. By select you can choose between RAMs.
This component is meant to be form of synchronization. Example first RAM is connected to first set of ports, writer performs actualizations on first RAM and reader reads data from second ram by second set of ports.
Then select is set and access is flipped. Reader now has access to RAM 0 and writer to RAM 1.
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.atomic.flipReg.
FlipRegister
[source]¶Bases: hwt.synthesizer.unit.Unit
Switchable register, there are two registers and two sets of ports, Each set of ports is every time connected to opposite reg. By select you can choose between regs.
This component is meant to be form of synchronization. Example first reg is connected to first set of ports, writer performs actualizations on first reg and reader reads data from second ram by second set of ports.
Then select is set and access is flipped. Reader now has access to reg 0 and writer to reg 1.
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only first obj of it’s class
Parameters: | priv – private data for this function (first object with class == obj.__class__) |
---|---|
Returns: | tuple (do serialize this object, next priv) where priv is private data for this function (first object with class == obj.__class__) |
hwtLib.mem.bramPortEndpoint.
BramPortEndpoint
(structTemplate, intfCls=<class 'hwt.interfaces.std.BramPort_withoutClk'>, shouldEnterFn=None)[source]¶Bases: hwtLib.abstract.busEndpoint.BusEndpoint
Delegate transaction from BrapmPort interface to interfaces for fields of specified structure
Attention: | interfaces are dynamically generated from names of fields in structure template |
---|
__init__
(structTemplate, intfCls=<class 'hwt.interfaces.std.BramPort_withoutClk'>, shouldEnterFn=None)[source]¶Parameters: |
|
---|
_getAddrStep
()¶Returns: | how many bits is one unit of address (f.e. 8 bits for char * pointer, 36 for 36 bit bram) |
---|
_getWordAddrStep
()¶Returns: | size of one word in unit of address |
---|
hwtLib.mem.bramPortSimMemSpaceMaster.
BramPortSimMemSpaceMaster
(bus, registerMap)[source]¶Bases: hwtLib.sim.abstractMemSpaceMaster.AbstractMemSpaceMaster
_read
(addr, size, onDone)[source]¶Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None
hwtLib.mem.cam.
Cam
[source]¶Bases: hwt.synthesizer.unit.Unit
Content addressable memory
Simple combinational version
MATCH_LATENCY = 1
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.clkSynchronizer.
ClkSynchronizer
[source]¶Bases: hwt.synthesizer.unit.Unit
Signal synchronization between two clock domains http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf
_config
()[source]¶Configure object parameters
hwtLib.mem.cuckooHashTable.
CInsertIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
_config
()[source]¶Configure object parameters
hwtLib.mem.cuckooHashTable.
CInsertIntfAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
Agent for CInsertIntf interface
hwtLib.mem.cuckooHashTable.
CuckooHashTable
(polynomials=[<class 'hwtLib.logic.crcPoly.CRC_32'>, <class 'hwtLib.logic.crcPoly.CRC_32C'>])[source]¶Bases: hwtLib.mem.hashTableCore.HashTableCore
Cuckoo hash uses more tables with different hash functions
Lookup is performed in all tables at once and if item is found in any table item is found otherwise item is not in tables. lookup time: O(1)
Insert has to first lookup if item is in any table. If there is such a item it is replaced. If there is any empty element item is stored there. If there is a valid item under this key in all tables. One is selected and it is replaced by current item. Insert process then repeats with this item.
Inserting into table does not have to be successful and in this case, fsm ends up in infinite loop and it will be reinserting items.
__init__
(polynomials=[<class 'hwtLib.logic.crcPoly.CRC_32'>, <class 'hwtLib.logic.crcPoly.CRC_32C'>])[source]¶Parameters: | polynomials – list of polynomials for crc hashers used in tables for each item in this list table will be instantiated |
---|
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
insetOfTablesDriver
(state, insertTargetOH, insertIndex, stash, isExternLookup)[source]¶Parameters: |
|
---|
hwtLib.mem.fifo.
Fifo
[source]¶Bases: hwt.synthesizer.unit.Unit
Generic fifo instance usually mapped to BRAM
Variables: |
|
---|
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.fifoAsync.
FifoAsync
[source]¶Bases: hwtLib.mem.fifo.Fifo
Asynchronous fifo using BRAM memory, based on: http://www.asic-world.com/examples/vhdl/asyn_fifo.html
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.hashTableCore.
HashTableCore
(polynome)[source]¶Bases: hwt.synthesizer.unit.Unit
Generic hash table, in block RAM there is a input key which is hashed ad this has is used as an index into memory item on this place is checked and returned on “lookupRes” interface (item does have to be found, see “found” flag in LookupResultIntf)
memory is an array of items in format
struct item {
bool vldFlag;
data_t data;
key_t key;
};
Variables: |
|
---|
_config
()[source]¶Configure object parameters
hwtLib.mem.hashTable_intf.
InsertIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
_config
()[source]¶Configure object parameters
hwtLib.mem.hashTable_intf.
InsertIntfAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
Simulation agent for .InsertIntf interface
hwtLib.mem.hashTable_intf.
LookupKeyIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.HandshakeSync
_config
()[source]¶Configure object parameters
hwtLib.mem.hashTable_intf.
LookupKeyIntfAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
Simulation agent for LookupKeyIntf interface
hwtLib.mem.hashTable_intf.
LookupResultIntf
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.interfaces.std.Handshaked
Interface for result of lookup in hash table
Variables: |
|
---|
_config
()[source]¶Configure object parameters
hwtLib.mem.hashTable_intf.
LookupResultIntfAgent
(intf)[source]¶Bases: hwt.interfaces.agents.handshaked.HandshakedAgent
Simulation agent for .LookupResultIntf data is stored in .data data format is tuple (hash, key, data, found) but some items can be missing depending on configuration of interface
hwtLib.mem.lutRam.
RAM64X1S
¶Bases: hwt.synthesizer.unit.Unit
_config
()¶_declr
()¶_impl
()¶_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Always decide not to serialize obj
Parameters: | priv – private data for this function first unit of this class |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.ram.
RamSingleClock
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.mem.ram.
Ram_dp
[source]¶Bases: hwtLib.mem.ram.Ram_sp
hwtLib.mem.ram.
Ram_sp
[source]¶Bases: hwt.synthesizer.unit.Unit
Write first variant
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.samples.arithmetic.cntr.
Cntr
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.arithmetic.selfRefCntr.
SelfRefCntr
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.arithmetic.twoCntrs.
TwoCntrs
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.arithmetic.widthCasting.
WidthCastingExample
[source]¶Bases: hwt.synthesizer.unit.Unit
Demonstration of how HWT width conversions are serialized into HDL
hwtLib.samples.axi.simpleAxiRegs.
SimpleAxiRegs
[source]¶Bases: hwt.synthesizer.unit.Unit
Axi litle mapped registers example, 0x0 - reg0 0x4 - reg1
_config
()[source]¶Configure object parameters
hwtLib.samples.builders.ethAddrUpdater.
EthAddrUpdater
[source]¶Bases: hwt.synthesizer.unit.Unit
This is example unit which reads dst and src addresses(MAC and IPv4) from ethernet frame stored in memory and writes this addresses in reverse direction into second frame.
_config
()[source]¶Configure object parameters
hwtLib.samples.builders.handshakedBuilderSimple.
HandshakedBuilderSimple
[source]¶Bases: hwt.synthesizer.unit.Unit
Simple example of HsBuilder which can build components for Handshaked interfaces
hwtLib.samples.builders.hsBuilderSplit.
HsBuilderSplit
[source]¶Bases: hwt.synthesizer.unit.Unit
Example of HsBuilder.split_* functions
hwtLib.samples.builders.pingResponder.
PingResponder
[source]¶Bases: hwt.synthesizer.unit.Unit
Listen for echo request on rx axi stream interface and respond with echo response on tx interface
Note: | incoming checksum is not checked |
---|---|
Attention: | you have to ping “ping -s 0 <ip>” because unit ignores additional data in packet and linux by defaults adds it |
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
connect_resp
(resp, forgeIn, sendingReply)[source]¶Connect response data on inputs of frame forge
Parameters: |
|
---|
icmp_checksum
(header)[source]¶Note: | we do not need to care about endianity because parser/forge will swap it for us and we can work with little endians only |
---|---|
Returns: | checksum for icmp header |
req_load
(parsed, regs, freeze)[source]¶Load request from parser input into registers
Parameters: |
|
---|---|
Attention: | dst and src are swapped |
hwtLib.samples.errors.accessingSubunitInternalIntf.
AccessingSubunitInternalIntf
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.inconsistentIntfDirection.
InconsistentIntfDirection
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.invalidTypeConnetion.
InvalidTypeConnetion
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.multipleDriversOfChildNet.
ExampleChild
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.multipleDriversOfChildNet.
MultipleDriversOfChildNet
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.multipleDriversOfChildNet.
MultipleDriversOfChildNet2
[source]¶Bases: hwtLib.samples.errors.multipleDriversOfChildNet.MultipleDriversOfChildNet
hwtLib.samples.errors.unusedSubunit.
ExampleChild
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.unusedSubunit.
UnusedSubunit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.errors.unusedSubunit.
UnusedSubunit2
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.hierarchy.groupOfBlockrams.
GroupOfBlockrams
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.hierarchy.netFilter.
Exporter
[source]¶Bases: hwt.synthesizer.interfaceLevel.emptyUnit.EmptyUnit
hwtLib.samples.hierarchy.netFilter.
Filter
[source]¶Bases: hwt.synthesizer.interfaceLevel.emptyUnit.EmptyUnit
hwtLib.samples.hierarchy.netFilter.
HeadFieldExtractor
[source]¶Bases: hwt.synthesizer.interfaceLevel.emptyUnit.EmptyUnit
hwtLib.samples.hierarchy.netFilter.
NetFilter
[source]¶Bases: hwt.synthesizer.unit.Unit
This unit has actually no functionality it is just example of hierarchical design.
_config
()[source]¶Configure object parameters
hwtLib.samples.hierarchy.netFilter.
PatternMatch
[source]¶Bases: hwt.synthesizer.interfaceLevel.emptyUnit.EmptyUnit
hwtLib.samples.hierarchy.simpleSubunit.
SimpleSubunit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.hierarchy.simpleSubunit2.
SimpleSubunit2
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.hierarchy.simpleSubunit3.
SimpleSubunit3
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.hierarchy.simpleSubunit3.
SimpleSubunit3TC
(methodName='runTest')[source]¶Bases: hwtLib.samples.hierarchy.simpleSubunit2.SimpleSubunit2TC
hwtLib.samples.hierarchy.unitToUnitConnection.
UnitToUnitConnection
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.hierarchy.unitToUnitConnection.
UnitToUnitConnectionTC
(methodName='runTest')[source]¶Bases: hwtLib.samples.hierarchy.simpleSubunit2.SimpleSubunit2TC
hwtLib.samples.intfArray.interfaceArray0.
InterfaceArraySample0
[source]¶Bases: hwt.synthesizer.unit.Unit
Sample unit with array interface (a and b) which is not using items of these array interfaces
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray0.
InterfaceArraySample0ConcatOnly
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray0.
InterfaceArraySample0SliceOnly
[source]¶Bases: hwt.synthesizer.unit.Unit
Sample unit with array interface a and three of output interfaces b
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray1.
InterfaceArraySample1
[source]¶Bases: hwt.synthesizer.unit.Unit
Example unit which contains two subuints (u0 and u1) and two array interfaces (a and b) first items of this interfaces are connected to u0 second to u1
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray1.
InterfaceArraySample1TC
(methodName='runTest')[source]¶Bases: hwt.simulator.simTestCase.SimTestCase
hwtLib.samples.intfArray.interfaceArray1.
SimpleSubunit
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray2.
InterfaceArraySample2
[source]¶Bases: hwt.synthesizer.unit.Unit
Example unit which contains two subunits (u0 and u1) and two array interfaces (a and b) first items of this interfaces are connected to u0 second to u1
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray2.
InterfaceArraySample2TC
(methodName='runTest')[source]¶Bases: hwt.simulator.simTestCase.SimTestCase
hwtLib.samples.intfArray.interfaceArray2.
SimpleSubunit
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray3.
InterfaceArraySample3
[source]¶Bases: hwt.synthesizer.unit.Unit
Sample unit with array interface (a and b) which is not using items of these array interfaces
_config
()[source]¶Configure object parameters
hwtLib.samples.intfArray.interfaceArray3.
InterfaceArraySample3TC
(methodName='runTest')[source]¶Bases: hwt.simulator.simTestCase.SimTestCase
hwtLib.samples.intfArray.interfaceArray3.
InterfaceArraySample3b
[source]¶Bases: hwtLib.samples.intfArray.interfaceArray3.InterfaceArraySample3
Sample unit with array interface (a and b) which is not using items of these array interfaces
hwtLib.samples.intfArray.interfaceArray4.
InterfaceArraySample4
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.intfArray.interfaceArray4.
InterfaceArraySample4TC
(methodName='runTest')[source]¶Bases: hwt.simulator.simTestCase.SimTestCase
hwtLib.samples.intfArray.interfaceArray4.
InterfaceArraySample4b
[source]¶Bases: hwtLib.samples.intfArray.interfaceArray4.InterfaceArraySample4
hwtLib.samples.intfArray.interfaceArray4.
InterfaceArraySample4c
[source]¶Bases: hwtLib.samples.intfArray.interfaceArray4.InterfaceArraySample4b
hwtLib.samples.intfArray.interfaceArray4.
InterfaceArraySample4d
[source]¶Bases: hwtLib.samples.intfArray.interfaceArray4.InterfaceArraySample4b
hwtLib.samples.mem.ram.
SimpleAsyncRam
[source]¶Bases: hwt.synthesizer.unit.Unit
Note that there is no such a thing in hw yet…
hwtLib.samples.mem.ram.
SimpleSyncRam
[source]¶note: | everything in hwtLib.samples is just example and it is usually more elegant way to do this |
---|
hwtLib.samples.mem.reg.
AsyncResetReg
[source]¶Bases: hwtLib.samples.mem.reg.DReg
hwtLib.samples.mem.reg.
DDR_Reg
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.mem.reg.
DReg
[source]¶Bases: hwt.synthesizer.unit.Unit
Basic d flip flop
Attention: | using this unit is pointless because HWToolkit can automatically generate such a register for any interface and datatype |
---|
hwtLib.samples.mem.reg.
DReg_asyncRst
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.mem.reg.
DoubleDReg
[source]¶Bases: hwt.synthesizer.unit.Unit
Attention: | using DReg unit instance is pointless because it can be instantiated by _reg in this unit |
---|
hwtLib.samples.mem.reg.
Latch
[source]¶Bases: hwt.synthesizer.unit.Unit
Example showing how to implement latch in hwt
hwtLib.samples.mem.reg.
OptimizedOutReg
[source]¶Bases: hwtLib.samples.mem.reg.DReg
hwtLib.samples.mem.rom.
SimpleRom
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.mem.rom.
SimpleSyncRom
[source]¶hwtLib.samples.operators.concat.
SimpleConcat
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
IndexingInernJoin
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
IndexingInernRangeSplit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
IndexingInernSplit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
SimpleIndexingJoin
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
SimpleIndexingRangeJoin
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.operators.indexing.
SimpleIndexingSplit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.constDriver.
ConstDriverUnit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.forLoopCntrl.
StaticForLoopCntrl
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.statements.fsm.
FsmExample
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
IfStatementPartiallyEnclosed
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatement
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatement2
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatement2b
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatement2c
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatementMergable
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatementMergable1
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.ifStm.
SimpleIfStatementMergable2
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.statements.switchStm.
SwitchStmUnit
[source]¶Bases: hwt.synthesizer.unit.Unit
Example which is using switch statement to create multiplexer
hwtLib.samples.statements.vldMaskConflictsResolving.
VldMaskConflictsResolving
[source]¶Bases: hwt.synthesizer.unit.Unit
Example how invalid value of condition does not matter when it has no effect on result
hwtLib.samples.hdlComments.
SimpleComentedUnit
[source]¶Bases: hwt.synthesizer.unit.Unit
This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment. Do not forget that class inheritance does apply for docstring as well.
hwtLib.samples.hdlComments.
SimpleComentedUnit2
[source]¶Bases: hwtLib.samples.hdlComments.SimpleComentedUnit
single line
hwtLib.samples.hdlComments.
SimpleComentedUnit3
[source]¶Bases: hwtLib.samples.hdlComments.SimpleComentedUnit2
dynamically generated, for example loaded from file or builded from unit content
hwtLib.samples.ipCoreCompatibleWrap.
ArrayIntfExample
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.parametrization.
ParametrizationExample
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.showcase0.
Showcase0
[source]¶Bases: hwt.synthesizer.unit.Unit
Every HW component class has to be derived from Unit class (any kind of inheritance supported)
_declr
()[source]¶In this function collecting of public interfaces is performed on every attribute assignment. Instances of Interface or Unit are recognized by Unit instance and are used as public interface of this unit.
Direction of interfaces is resolved by access from inside of this unit and you do not have to care about it.
hwtLib.samples.simple2withNonDirectIntConnection.
Simple2withNonDirectIntConnection
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.samples.simpleAxiStream.
SimpleUnitAxiStream
[source]¶Bases: hwt.synthesizer.unit.Unit
Example of unit with axi stream interface
_config
()[source]¶Configure object parameters
hwtLib.samples.simpleWithNonDirectIntConncetion.
SimpleWithNonDirectIntConncetion
[source]¶Bases: hwt.synthesizer.unit.Unit
Example of fact that interfaces does not have to be only extern the can be used even for connection inside unit
hwtLib.samples.simpleWithParam.
SimpleUnitWithParam
[source]¶Bases: hwt.synthesizer.unit.Unit
Simple parametrized unit.
_config
()[source]¶Configure object parameters
hwtLib.samples.timers.
DynamicCounterInstancesExample
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.timers.
TimerInfoTest
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.samples.timers.
TimerTC
(methodName='runTest')[source]¶Bases: hwt.simulator.simTestCase.SimTestCase
hwtLib.samples.timers.
TimerTestUnit
[source]¶Bases: hwt.synthesizer.unit.Unit
hwtLib.sim.abstractMemSpaceMaster.
AbstractMemSpaceMaster
(bus, registerMap)[source]¶Bases: hwtLib.sim.abstractMemSpaceMaster.MemorySpaceItemStruct
Abstraction over bus interface which converts it to memory space from where you can read or write
_read
(addr, size, onDone=None)[source]¶Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None
hwtLib.sim.abstractMemSpaceMaster.
MemorySpaceItem
(memHandler, transTmpl, offset=0)[source]¶Bases: object
Abstraction over place in memory, allows you read and write data to/from this space
hwtLib.sim.abstractMemSpaceMaster.
MemorySpaceItemArr
(memHandler, transTmpl, offset=0)[source]¶Bases: object
Abstraction over place in memory, allows you read and write data to/from this space
hwtLib.spi.intf.
QSPI
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.spi.intf.SpiTristate
SPI interface with 4 tristate data wires
hwtLib.spi.intf.
Spi
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
Bare SPI interface (Serial peripheral interface)
_config
()[source]¶Configure object parameters
hwtLib.spi.intf.
SpiAgent
(intf, allowNoReset=False)[source]¶Bases: hwt.simulator.agentBase.SyncAgentBase
Simulation agent for SPI interface
Variables: |
|
---|
chipSelects, rxData and txData are lists of integers
BITS_IN_WORD
= 8¶__init__
(intf, allowNoReset=False)[source]¶Initialize self. See help(type(self)) for accurate signature.
hwtLib.spi.intf.
SpiTristate
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.spi.intf.Spi
SPI interface where mosi and miso signal are merged into one tristate wire
hwtLib.spi.master.
SpiCntrlData
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectional
HandshakedBiDirectional interface with last and slave signal added. If last=1 slave will be deselected and initial slave select wait will be. Slave selects the slave where data should be read from and written to.
hwtLib.spi.master.
SpiCntrlDataAgent
(intf)[source]¶Bases: hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectionalAgent
hwtLib.spi.master.
SpiMaster
[source]¶Bases: hwt.synthesizer.unit.Unit
Master for SPI interface
Variables: |
|
---|---|
Attention: | this implementation expects that slaves are reading data on rising edge of SPI clk and data from slaves are ready on risign edge as well and SPI clk is kept high in idle (most of them does but there are some exceptions) |
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
hwtLib.structManipulators.arrayBuff_writer.
ArrayBuff_writer
[source]¶Bases: hwt.synthesizer.unit.Unit
Collect items and send them over wDatapump when buffer is full or on timeout Cyclically writes items into array over wDatapump Maximum overlap of transactions is 1
[TODO] better fit of items on bus [TODO] fully pipeline
items -> buff -> internal logic -> axi datapump
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
_serializeDecision
(parentUnit, obj, isDeclaration, priv)¶Decide to serialize only objs with uniq parameters and class
Parameters: | priv – private data for this function ({frozen_params: obj}) |
---|---|
Returns: | tuple (do serialize this object, next priv) |
hwtLib.structManipulators.arrayItemGetter.
ArrayItemGetter
[source]¶Bases: hwt.synthesizer.unit.Unit
Get specific item from array by index
_config
()[source]¶Configure object parameters
hwtLib.structManipulators.cLinkedListReader.
CLinkedListReader
[source]¶Bases: hwt.synthesizer.unit.Unit
This unit reads items from (circular) linked list like structure
struct node {
item_t items[ITEMS_IN_BLOCK],
struct node * next;
};
synchronization is obtained by rdPtr/wrPtr (tail/head) pointer baseAddr is address of actual node
Attention: | device reads only chunks of size <= BUFFER_CAPACITY/2, |
---|
_config
()[source]¶Configure object parameters
hwtLib.structManipulators.cLinkedListWriter.
CLinkedListWriter
[source]¶Bases: hwt.synthesizer.unit.Unit
This unit writes items to (circular) linked list like structure (List does not necessary need to be circular but space is specified by two pointers like in circular queue)
struct node {
item_t items[ITEMS_IN_BLOCK],
struct node * next;
};
synchronization is obtained by rdPtr/wrPtr (tail/head) pointer baseAddr is address of actual node
Attention: | device writes chunks of max size <= BUFFER_CAPACITY/2 |
---|---|
Attention: | next addr is downloaded on background when items are uploaded (= has to be set when this unit enters this block) |
Note: | wrPtr == rdPtr => queue is empty and there is (2^PTR_WIDTH) - 1 of empty space wrPtr == rdPtr+1 => queue is full wrPtr+1 == rdPtr => there is (2^PTR_WIDTH) - 2 of empty space spaceToWrite = rdPtr - wrPtr - 1 (with uint16_t) |
_config
()[source]¶Configure object parameters
_declr
()[source]¶declarations
baseAddrLogic
(nextBlockTransition_in)[source]¶Logic for downloading address of next block
Parameters: | nextBlockTransition_in – signal which means that baseIndex should be changed to nextBaseIndex if nextBaseAddrReady is not high this signal has no effect (= regular handshake) |
---|---|
Returns: | (baseIndex, nextBaseIndex, nextBaseReady is ready and nextBlockTransition_in can be used) |
hwtLib.structManipulators.mmu_2pageLvl.
MMU_2pageLvl
[source]¶Bases: hwt.synthesizer.unit.Unit
MMU where parent page table is stored in ram this unit and only items from leaf page tables are download on each request over rDatapump interface
Attention: | if item in pagetable is BAD_PHYS_ADDR output signal segfault becomes 1 and unit will stop working |
---|---|
Attention: | rootPageTable has to be initialized before first request over virtIn interface |
Attention: | rootPageTable has write only access |
Attention: | use value -1 to mark that page is not mapped, it will result in segfault signal asserted high when this address is accessed |
_config
()[source]¶Configure object parameters
hwtLib.structManipulators.structReader.
StructReader
(structT, tmpl=None, frames=None)[source]¶Bases: hwtLib.amba.axis_comp.frameParser.AxiS_frameParser
This unit downloads required structure fields over rDatapump interface from address specified by get interface
Variables: |
|
---|---|
Attention: | interfaces of field will not send data in same time |
Note: | names in the picture are just illustrative |
---|
__init__
(structT, tmpl=None, frames=None)[source]¶Parameters: |
|
---|---|
Note: | if tmpl and frames are None they are resolved from structT parseTemplate |
Note: | this unit can parse sequence of frames, if they are specified by “frames” |
Attention: | interfaces for each field in struct will be dynamically created |
Attention: | structT can not contain fields with variable size like HStream |
_config
()[source]¶Configure object parameters
hwtLib.structManipulators.structWriter.
StructWriter
(structT, tmpl=None, frames=None)[source]¶Bases: hwtLib.structManipulators.structReader.StructReader
Write struct specified in constructor over wDatapump interface on address specified over set interface
Variables: |
|
---|
Note: | names in the picture are just illustrative |
---|
_config
()[source]¶Configure object parameters
hwtLib.types.net.arp.
ARP_HW_TYPE
[source]¶Bases: object
ARP_SEC
= 32¶ETHERNET
= 1¶FIBRE_CHANNEL
= 18¶FRAME_RELAY
= 15¶INIFNIBAND
= 32¶IP_SEC_TUNNEL
= 31¶hwtLib.types.net.arp.
ARP_OPTCODE
[source]¶Bases: object
ARP_NAK
= 10¶IN_ARP_REPLY
= 9¶IN_ARP_REQUEST
= 8¶MAPOS_UNARP
= 23¶MARS
[source]¶Bases: object
GROUPLIST_REPLY
= 21¶GROUPLIST_REQUEST
= 20¶JOIN
= 14¶LEAVE
= 15¶MSERV
= 13¶MULTI
= 12¶NAK
= 16¶REDIRECT_MAP
= 22¶REQUEST
= 11¶SJOIN
= 18¶SLEAVE
= 19¶UNSERV
= 17¶OP_EXP1
= 24¶OP_EXP2
= 25¶REPLY
= 2¶REQUEST
= 1¶REQUEST_REVERSE
= 3¶hwtLib.types.net.ip.
IP_PROTOCOL
[source]¶Bases: object
EGP
= 8¶ENCAP
= 41¶ETHERIP
= 97¶GGP
= 3¶HOPOPT
= 0¶ICMP
= 1¶IGMP
= 2¶IGP
= 9¶IPIP
= 94¶IPv4
= 4¶IPv6_ICMP
= 58¶IPv6_frag
= 44¶IPv6_noNxt
= 59¶IPv6_opts
= 60¶IPv6_route
= 43¶L2TP
= 115¶OSPF
= 89¶QNX
= 106¶SCTP
= 132¶SMP
= 121¶TCP
= 6¶UDP
= 17¶hwtLib.uart.intf.
IP_Uart
[source]¶Bases: hwt.serializer.ip_packager.interfaces.intfConfig.IntfConfig
hwtLib.uart.intf.
Uart
(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]¶Bases: hwt.synthesizer.interface.Interface
hwtLib.uart.rx.
UartRx
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters
hwtLib.uart.tx.
UartTx
[source]¶Bases: hwt.synthesizer.unit.Unit
_config
()[source]¶Configure object parameters