hwtLib.amba.axis_comp.frame_join package

Submodules

hwtLib.amba.axis_comp.frame_join.input_reg module

class hwtLib.amba.axis_comp.frame_join.input_reg.FrameJoinInputReg(hdl_name_override: Optional[str] = None)

Bases: Unit

Pipeline of registers for AxiStream with keep mask and flushing

HDL params

• REG_CNT - default value 2 of type int

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value True of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• regs_0 - of type hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf - MASTER

• regs_1 - of type hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf - MASTER

• keep_masks_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - SLAVE

• keep_masks_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - SLAVE

• ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

class hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)

Bases: Interface

HDL params

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER

• keep - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER

• relict - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

• last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER