hwtLib.mem.atomic package¶
Submodules¶
hwtLib.mem.atomic.flipCntr module¶
- class hwtLib.mem.atomic.flipCntr.FlipCntr(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Counter with FlipRegister which is form memory with atomic access
interface doFilip drives switching of memories in flip register dataIn has higher priority than doIncr
- HDL params
DATA_WIDTH - default value 18 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
doIncr - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
doFlip - of type hwt.interfaces.std.HandshakeSync - SLAVE
data - of type hwt.interfaces.std.RegCntrl - SLAVE
- HDL components
cntr - of type hwtLib.mem.atomic.flipReg.FlipRegister
hwtLib.mem.atomic.flipRam module¶
- class hwtLib.mem.atomic.flipRam.FlipRam(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Switchable RAM, there are two memories and two sets of ports, Each set of ports is every time connected to opposite ram. By select you can choose between RAMs.
This component is meant to be form of synchronization. Example first RAM is connected to first set of ports, writer performs actualizations on first RAM and reader reads data from second ram by second set of ports.
Then select is set and access is flipped. Reader now has access to RAM 0 and writer to RAM 1.
- HDL params
ADDR_WIDTH - default value 10 of type int
DATA_WIDTH - default value 64 of type int
PORT_CNT - default value 1 of type int
HAS_BE - default value False of type bool
MAX_BLOCK_DATA_WIDTH - default value None of type None
INIT_DATA - default value None of type None
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
firstA - of type hwt.interfaces.std.BramPort_withoutClk - SLAVE
secondA - of type hwt.interfaces.std.BramPort_withoutClk - SLAVE
select_sig - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
- HDL components
ram0 - of type hwtLib.mem.ram.RamSingleClock
ram1 - of type hwtLib.mem.ram.RamSingleClock
hwtLib.mem.atomic.flipReg module¶
- class hwtLib.mem.atomic.flipReg.FlipRegister(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Switchable register, there are two registers and two sets of ports, Each set of ports is every time connected to opposite reg. By select you can choose between regs.
This component is meant to be form of synchronization. Example first reg is connected to first set of ports, writer performs actualizations on first reg and reader reads data from second ram by second set of ports.
Then select is set and access is flipped. Reader now has access to reg 0 and writer to reg 1.
- HDL params
DATA_WIDTH - default value 32 of type int
DEFAULT_VAL - default value 0 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
first - of type hwt.interfaces.std.RegCntrl - SLAVE
second - of type hwt.interfaces.std.RegCntrl - SLAVE
select_sig - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE