hwtLib.peripheral.uart package¶
Submodules¶
hwtLib.peripheral.uart.intf module¶
- class hwtLib.peripheral.uart.intf.IP_Uart[source]¶
Bases:
IntfIpMeta
- library¶
- name¶
- vendor¶
- version¶
- class hwtLib.peripheral.uart.intf.Uart(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
Base UART interface, also known as Serial or COM.
- HDL IO
rx - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
tx - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
hwtLib.peripheral.uart.rx module¶
- class hwtLib.peripheral.uart.rx.UartRx(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
UART Rx channel controller
- HDL params
FREQ - default value 100000000 of type int
BAUD - default value 115200 of type int
OVERSAMPLING - default value 16 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataOut - of type hwt.interfaces.std.VldSynced - MASTER
rxd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
hwtLib.peripheral.uart.tx module¶
- class hwtLib.peripheral.uart.tx.UartTx(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
UART Tx channel controller
- HDL params
FREQ - default value 100000000 of type int
BAUD - default value 115200 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
txd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER