Source code for hwtLib.examples.simple

#!/usr/bin/env python3
# -*- coding: utf-8 -*-

from hwt.interfaces.std import Signal
from hwt.synthesizer.unit import Unit


[docs]class SimpleUnit(Unit): """ In order to create a new unit you have to make new class derived from Unit. You can use sphinx-hwt plugin for sphinx document generator to generate interactive schematic and documentation. Schematic is generated by directive bellow. .. hwt-autodoc:: """
[docs] def _declr(self): """ _declr() is like header of Unit. There you have to declare things which should be visible from outside. """ # interfaces "a" and "b" are accessible from outside when declared # in _declr method, this means they will be interfaces of Entity/Module # and parent unit can connect signals to this interfaces # note that interfaces has to be properties of this object # which is kind of registration and without it, they can not be discovered self.a = Signal() # "b" is output and has to be marked as master then self.b = Signal()._m()
[docs] def _impl(self): """ _impl() is like body of unit. Logic and connections are specified i`qn this function. """ # call operator creates assignment. First parameter is source rest # are destinations. self.b(self.a) # a drives b, "()" because "=" can not be overriden
if __name__ == "__main__": # alias python main function # to_rtl_str can be imported anywhere but we prefer to import it only # when this script is running as main from hwt.synthesizer.utils import to_rtl_str from hwt.serializer.vhdl import Vhdl2008Serializer # there are other serializers ... # from hwt.serializer.hwt import HwtSerializer # from hwt.serializer.simModel import SimModelSerializer # from hwt.serializer.verilog import VerilogSerializer # we create instance of our unit u = SimpleUnit() # to_rtl_str() returns hdl string, you can also generate files with to_rtl, IP-xact packages with IpPackager print(to_rtl_str(u, serializer_cls=Vhdl2008Serializer)) # expected Output (without # ofcourse) # -- In order to create a new unit you have to make new class derived from Unit. # -- # -- You can use sphinx-hwt plugin for sphinx document generator # -- to generate interactive schematic and documentation. # -- Schematic is generated by directive bellow. # LIBRARY IEEE; # USE IEEE.std_logic_1164.ALL; # USE IEEE.numeric_std.ALL; # # ENTITY SimpleUnit IS # PORT (a : IN STD_LOGIC; # b : OUT STD_LOGIC # ); # END ENTITY; # # ARCHITECTURE rtl OF SimpleUnit IS # # BEGIN # # b <= a; # # END ARCHITECTURE;