hwtLib.common_nonstd_interfaces package¶

A package dedicated to commonly used interfaces wich are not part of any standard. This usually involves trivial interfaces which do have some well defined meaning.

Submodules¶

hwtLib.common_nonstd_interfaces.addr_data_hs module¶

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataBitMaskHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: AddrDataHs

HDL params

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
mask - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakeSync

Simple handshaked interface with address and data signal

HDL params

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataMaskHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataVldAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataVldHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: AddrDataHs

HDL params

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
vld_flag - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.common_nonstd_interfaces.addr_data_hs_bidir module¶

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrInDataOutHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakedBiDirectional

HDL params

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrInDataOutHsAgent(sim, intf)[source]¶

Bases: HandshakedBiDirectionalAgent

Simulation agent for AddrDataOutInHs interface

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrInOutDataInHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakedBiDirectional

HDL params

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO

addrIn - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
addrOut - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrInOutDataInHsAgent(sim, intf)[source]¶

Bases: HandshakedBiDirectionalAgent

Simulation agent for AddrInOutDataInHs interface

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrOutDataInHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakedBiDirectional

HDL params

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_data_hs_bidir.AddrOutDataInHsAgent(sim, intf)[source]¶

Bases: HandshakedBiDirectionalAgent

Simulation agent for AddrOutDataInHs interface

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

hwtLib.common_nonstd_interfaces.addr_data_hs_to_Axi module¶

class hwtLib.common_nonstd_interfaces.addr_data_hs_to_Axi.AddrDataHs_to_Axi(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶

Bases: BusBridge

Bridge AddrDataHs,RamHsR -> Axi3/4

read delay: 1, transaction overlap 0
write delay: 1, transaction overlap 0

Variables

~.S_ADDR_STEP – number of bites per step on AddrDataHs,RamHsR interfaces
~.M_DATA_WIDTH – data width for AXI interface
~.M_ID_WIDTH – id width for AXI interface
~.M_ADDR_OFFSET – address offset value for axi interface

HDL params

ADDR_WIDTH - default value 16 of type int
DATA_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
S_ADDR_STEP - default value 16 of type int
S_ADDR_WIDTH - default value 15 of type int
S_DATA_WIDTH - default value 16 of type int
M_ADDR_OFFSET - default value 0 of type int
MAX_TRANS_OVERLAP - default value 64 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_r - of type hwtLib.handshaked.ramAsHs.RamHsR - SLAVE
s_w - of type hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHs - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER

HDL components

axi_buff - of type hwtLib.amba.axi_comp.buff.AxiBuff
gen_r_tmp_parser_0 - of type hwtLib.amba.axis_comp.frame_parser._parser.AxiS_frameParser
gen__select_fifo_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinPrioritized.HsJoinPrioritized
deparsed_deparser_0 - of type hwtLib.amba.axis_comp.frame_deparser._deparser.AxiS_frameDeparser
w_data_reg - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶

addr_defaults(a: Axi4_addr)[source]¶

connect_addr(src, dst)[source]¶

connect_r(s_r: RamHsR, axi: Axi4, r_cntr: RtlSignal, CNTR_MAX: int, in_axi_t: Union[HStruct, HUnion])[source]¶

connect_w(s_w: AddrDataHs, axi: Axi4, w_cntr: RtlSignal, CNTR_MAX: int, in_axi_t: HStruct)[source]¶

generate_in_axi_type()[source]¶

split_subaddr(addr: RtlSignal)[source]¶

hwtLib.common_nonstd_interfaces.addr_data_hs_to_Axi.example_AddrDataHs_to_Axi()[source]¶: Download a 512b word over 64b interface

hwtLib.common_nonstd_interfaces.addr_hs module¶

class hwtLib.common_nonstd_interfaces.addr_hs.AddrHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakeSync

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.addr_hs.AddrHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

hwtLib.common_nonstd_interfaces.data_mask_last_hs module¶

class hwtLib.common_nonstd_interfaces.data_mask_last_hs.DataMaskHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

Simulation agent for DataMaskLastHs interface.

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.data_mask_last_hs.DataMaskLastHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

Handshaked interface with data, mask, last signal.

HDL params

MASK_GRANULARITY - default value 8 of type int
DATA_WIDTH - default value 64 of type int

HDL IO

data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
mask - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.common_nonstd_interfaces.index_key_hs module¶

class hwtLib.common_nonstd_interfaces.index_key_hs.IndexKeyHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

HDL params

INDEX_WIDTH - default value 4 of type int
KEY_WIDTH - default value 4 of type int

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
key - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
index - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.index_key_hs.IndexKeyHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data() → Union[Tuple[int, int], int][source]¶: extract data from interface

set_data(data: Union[Tuple[int, int], int])[source]¶: write data to interface

class hwtLib.common_nonstd_interfaces.index_key_hs.IndexKeyInHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

HDL params

INDEX_WIDTH - default value 4 of type int
KEY_WIDTH - default value 4 of type int

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
key - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE (Master=IN)
index - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.common_nonstd_interfaces.index_key_hs.IndexKeyInHsAgent(sim, intf)[source]¶

Bases: HandshakedBiDirectionalAgent

get_data() → Union[Tuple[int, int], int][source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data: Union[Tuple[int, int], int])[source]¶: write data to interface