hwtLib.spi package

Submodules

hwtLib.spi.intf module

class hwtLib.spi.intf.QSPI(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]

Bases: hwtLib.spi.intf.SpiTristate

SPI interface with 4 tristate data wires

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
class hwtLib.spi.intf.Spi(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Bare SPI interface (Serial peripheral interface)

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)
  • _declr method is called after _config
  • if this object is Unit all interfaces are threaten as externally accessible interfaces if this object is Interface all subinterfaces are loaded
_initSimAgent()[source]
class hwtLib.spi.intf.SpiAgent(intf, allowNoReset=False)[source]

Bases: hwt.simulator.agentBase.SyncAgentBase

Simulation agent for SPI interface

Variables:
  • txData – data to transceive container
  • rxData – received data
  • chipSelects – values of chip select

chipSelects, rxData and txData are lists of integers

BITS_IN_WORD = 8
__init__(intf, allowNoReset=False)[source]

Initialize self. See help(type(self)) for accurate signature.

driverRx(sim)[source]
driverTx(s)[source]
getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

mergeBits(bits)[source]
monitorRx(sim)[source]
monitorTx(sim)[source]
readRxSig(sim, sig)[source]
setEnable(en)[source]
splitBits(v)[source]
writeTxSig(sim, sig)[source]
class hwtLib.spi.intf.SpiTristate(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]

Bases: hwtLib.spi.intf.Spi

SPI interface where mosi and miso signal are merged into one tristate wire

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)
  • _declr method is called after _config
  • if this object is Unit all interfaces are threaten as externally accessible interfaces if this object is Interface all subinterfaces are loaded

hwtLib.spi.master module

class hwtLib.spi.master.SpiCntrlData(masterDir=<DIRECTION.OUT: 1>, asArraySize=None, loadConfig=True)[source]

Bases: hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectional

HandshakedBiDirectional interface with last and slave signal added. If last=1 slave will be deselected and initial slave select wait will be. Slave selects the slave where data should be read from and written to.

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)
  • _declr method is called after _config
  • if this object is Unit all interfaces are threaten as externally accessible interfaces if this object is Interface all subinterfaces are loaded
_initSimAgent()[source]
class hwtLib.spi.master.SpiCntrlDataAgent(intf)[source]

Bases: hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectionalAgent

doRead(s)[source]

extract data from interface

doWrite(s, data)[source]

write data to interface

class hwtLib.spi.master.SpiMaster[source]

Bases: hwt.synthesizer.unit.Unit

Master for SPI interface

Variables:
  • SPI_FREQ_PESCALER – frequency prescaler to get SPI clk from main clk (Param)
  • SS_WAIT_CLK_TICKS – number of SPI ticks to wait with SPI clk activation after slave select
  • HAS_TX – if set true write part will be instantiated
  • HAS_RX – if set true read part will be instantiated
Attention:

this implementation expects that slaves are reading data on rising edge of SPI clk and data from slaves are ready on risign edge as well and SPI clk is kept high in idle (most of them does but there are some exceptions)
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)
  • _declr method is called after _config
  • if this object is Unit all interfaces are threaten as externally accessible interfaces if this object is Interface all subinterfaces are loaded
_impl()[source]

implementations

  • implement functionality of design there
  • called after _declr
readPart(readTick)[source]
spiClkGen(requiresInitWait, en)[source]

create clock generator for SPI writeTick is 1 on falling edge of spi clk readTick is 1 on rising edge of spi clk

Returns:tuple of tick signals (if data should be send, if data should be read)
writePart(writeTick, isLastTick, data)[source]

Module contents