Source code for hwtLib.amba.ace

from hwt.interfaces.std import VectSignal, Signal
from hwt.synthesizer.param import Param
from hwtLib.amba.axi3Lite import Axi3Lite_bAgent
from hwtLib.amba.axi4 import Axi4, Axi4_addr
from hwtLib.amba.axi_intf_common import Axi_hs
from ipCorePackager.constants import DIRECTION
from pycocotb.hdlSimulator import HdlSimulator


[docs]class DOMAIN(): NON_SHARABLE = 0 INNER_SHARABLE = 1 OUTER_SHARABLE = 2 SYSTEM = 3
[docs]class CACHE(): DEVICE = 0 NON_CACHEABLE = 0b0011 WRITE_THROUGH = 0b0111 WRITE_BACK = 0b1011
[docs]class BAR(): NORMAL = 0b00 BARRIER = 0b01 IGNORE = 0b10 SYNCHRONIZATION = 0b11
[docs]class AR_MODE():
[docs] class NO_SNOOP():
[docs] class READ(): NON = (BAR.NORMAL, DOMAIN.NON_SHARABLE, 0b0000) SYSTEM = (BAR.NORMAL, DOMAIN.SYSTEM, 0b0000)
[docs] class COHERENT():
[docs] class READ_ONCE(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b0000) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b0000)
[docs] class READ_SHARED(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b0001) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b0001)
[docs] class READ_CLEAN(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b0010) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b0010)
[docs] class READ_NOT_SHARED_DIRTY(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b0011) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b0011)
[docs] class READ_UNIQUE(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b0111) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b0111)
[docs] class CLEAN_UNIQUE(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1011) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1011)
[docs] class MAKE_UNIQUE(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1100) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1100)
[docs] class CACHE_MAINTENANCE():
[docs] class CLEAN_SHARED(): NON = (BAR.NORMAL, DOMAIN.NON_SHARABLE, 0b1000) INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1000) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1000)
[docs] class CLEAN_INVALID(): NON = (BAR.NORMAL, DOMAIN.NON_SHARABLE, 0b1001) INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1001) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1001)
[docs] class MAKE_INVALID(): NON = (BAR.NORMAL, DOMAIN.NON_SHARABLE, 0b1101) INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1101) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1101)
[docs] class BARRIER(): NON = (BAR.BARRIER, DOMAIN.NON_SHARABLE, 0b0000) INNER = (BAR.BARRIER, DOMAIN.INNER_SHARABLE, 0b0000) OUTER = (BAR.BARRIER, DOMAIN.OUTER_SHARABLE, 0b0000) SYSTEM = (BAR.BARRIER, DOMAIN.SYSTEM, 0b0000)
[docs] class DVM():
[docs] class COMPLETE(): INNER = (BAR.NORMAL, DOMAIN.INNER_SHARABLE, 0b1110) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1110)
[docs] class MESSAGE(): INNER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1111) OUTER = (BAR.NORMAL, DOMAIN.OUTER_SHARABLE, 0b1111)
[docs]def setAceArMode(arbar, ardomain, arsnoop, transactionType): bar, dom, snoop = transactionType arbar(bar) ardomain(dom) arsnoop(snoop)
[docs]class Ace_addr(Axi4_addr):
[docs] def _declr(self): Axi4_addr._declr(self) self.domain = VectSignal(2) self.region = VectSignal(4) self.snoop = VectSignal(3) self.bar = VectSignal(2)
[docs]class AceSnoop_addr(Axi_hs):
[docs] def _config(self): self.SNOOP_ADDR_WIDTH = Param(32)
[docs] def _declr(self): self.addr = VectSignal(self.ADDR_WIDTH) self.snoop = VectSignal(4) self.prot = VectSignal(3) Axi_hs._declr(self)
[docs]class AceSnoop_resp(Axi_hs):
[docs] def _declr(self): self.resp = VectSignal(4) Axi_hs._declr(self)
[docs] def _initSimAgent(self, sim: HdlSimulator): self._ag = Axi3Lite_bAgent(sim, self)
[docs]class AceSnoop_data(Axi_hs):
[docs] def _config(self): self.SNOOP_DATA_WIDTH = Param(32)
[docs] def _declr(self): self.data = VectSignal(self.SNOOP_DATA_WIDTH) self.last = Signal() Axi_hs._declr(self)
[docs]class Ace(Axi4): """ :ivar ac: Coherent address channel. snoop address input to the master :ivar cr: Coherent response channel. used by the master to signal the response to snoops to the interconnect :ivar cd: Coherent data channel. output from the master to transfer snoop data """ AW_CLS = Ace_addr AR_CLS = Ace_addr
[docs] def _config(self): Axi4._config(self) self.SNOOP_ADDR_WIDTH = Param(32) self.SNOOP_DATA_WIDTH = Param(32)
[docs] def _declr(self): super(Ace, self)._declr() with self._paramsShared(): self.ac = AceSnoop_addr(masterDir=DIRECTION.IN) self.cr = AceSnoop_resp() self.cd = AceSnoop_data()
[docs] def _initSimAgent(self, sim: HdlSimulator): raise NotImplementedError()
[docs] def _getIpCoreIntfClass(self): raise NotImplementedError()