hwtLib.amba package¶
This package is dedicated to component and utilities related to ARM AMBA interfaces.
This icludes:
AMBA AXI3
AMBA AXI3-lite
AMBA AXI4
AMBA AXI4-lite
AMBA AXI4-stream
AMBA ACE
and others
Available specifications:
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
https://static.docs.arm.com/ihi0051/a/IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf
Subpackages¶
- hwtLib.amba.axiLite_comp package
- hwtLib.amba.axi_comp package
- Subpackages
- hwtLib.amba.axi_comp.cache package
- Submodules
- hwtLib.amba.axi_comp.cache.addrTypeConfig module
- hwtLib.amba.axi_comp.cache.cacheWriteAllocWawOnlyWritePropagating module
- hwtLib.amba.axi_comp.cache.lru_array module
- hwtLib.amba.axi_comp.cache.pseudo_lru module
- hwtLib.amba.axi_comp.cache.tag_array module
- hwtLib.amba.axi_comp.cache.utils module
- hwtLib.amba.axi_comp.interconnect package
- Submodules
- hwtLib.amba.axi_comp.interconnect.base module
- hwtLib.amba.axi_comp.interconnect.common module
- hwtLib.amba.axi_comp.interconnect.matrix module
- hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar module
- hwtLib.amba.axi_comp.interconnect.matrixCrossbar module
- hwtLib.amba.axi_comp.interconnect.matrixR module
- hwtLib.amba.axi_comp.interconnect.matrixW module
- hwtLib.amba.axi_comp.lsu package
- Submodules
- hwtLib.amba.axi_comp.lsu.fifo_oooread module
- hwtLib.amba.axi_comp.lsu.interfaces module
- hwtLib.amba.axi_comp.lsu.read_aggregator module
- hwtLib.amba.axi_comp.lsu.store_queue_write_propagating module
- hwtLib.amba.axi_comp.lsu.write_aggregator module
- hwtLib.amba.axi_comp.lsu.write_aggregator_write_dispatcher module
- hwtLib.amba.axi_comp.oooOp package
- hwtLib.amba.axi_comp.sim package
- hwtLib.amba.axi_comp.cache package
- Submodules
- hwtLib.amba.axi_comp.buff module
- hwtLib.amba.axi_comp.buff_cdc module
- hwtLib.amba.axi_comp.builder module
- hwtLib.amba.axi_comp.resize module
- hwtLib.amba.axi_comp.slave_timeout module
- hwtLib.amba.axi_comp.static_remap module
- hwtLib.amba.axi_comp.stream_to_mem module
- hwtLib.amba.axi_comp.tester module
- hwtLib.amba.axi_comp.to_axiLite module
- hwtLib.amba.axi_comp.virtualDma module
- Subpackages
- hwtLib.amba.axis_comp package
- Subpackages
- Submodules
- hwtLib.amba.axis_comp.base module
- hwtLib.amba.axis_comp.builder module
- hwtLib.amba.axis_comp.cdc module
- hwtLib.amba.axis_comp.en module
- hwtLib.amba.axis_comp.fifo module
- hwtLib.amba.axis_comp.fifoCopy module
- hwtLib.amba.axis_comp.fifoDrop module
- hwtLib.amba.axis_comp.fifoMeasuring module
- hwtLib.amba.axis_comp.fifo_async module
- hwtLib.amba.axis_comp.frameGen module
- hwtLib.amba.axis_comp.joinPrioritized module
- hwtLib.amba.axis_comp.reg module
- hwtLib.amba.axis_comp.resizer module
- hwtLib.amba.axis_comp.splitCopy module
- hwtLib.amba.axis_comp.splitSelect module
- hwtLib.amba.axis_comp.storedBurst module
- hwtLib.amba.axis_comp.strformat module
- hwtLib.amba.axis_comp.strformat_fn module
- hwtLib.amba.datapump package
- hwtLib.amba.sim package
Submodules¶
hwtLib.amba.ace module¶
- class hwtLib.amba.ace.AR_MODE[source]¶
Bases:
object
- class BARRIER[source]¶
Bases:
object
- INNER = (1, 1, 0)¶
- NON = (1, 0, 0)¶
- OUTER = (1, 2, 0)¶
- SYSTEM = (1, 3, 0)¶
- class hwtLib.amba.ace.Ace(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi4
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
SNOOP_ADDR_WIDTH - default value 32 of type int
SNOOP_DATA_WIDTH - default value 32 of type int
- HDL IO
ar - of type hwtLib.amba.ace.Ace_addr - MASTER
r - of type hwtLib.amba.axi4.Axi4_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.ace.Ace_addr - MASTER
w - of type hwtLib.amba.axi4.Axi4_w - MASTER
b - of type hwtLib.amba.axi4.Axi4_b - SLAVE (Master=IN)
ac - of type hwtLib.amba.ace.AceSnoop_addr - SLAVE (Master=IN) Coherent address channel. snoop address input to the master
cr - of type hwtLib.amba.ace.AceSnoop_resp - MASTER Coherent response channel. used by the master to signal the response to snoops to the interconnect
cd - of type hwtLib.amba.ace.AceSnoop_data - MASTER Coherent data channel. output from the master to transfer snoop data
- class hwtLib.amba.ace.AceSnoop_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL params
SNOOP_ADDR_WIDTH - default value 32 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
snoop - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.ace.AceSnoop_data(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL params
SNOOP_DATA_WIDTH - default value 32 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.ace.AceSnoop_resp(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL IO
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.ace.Ace_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi4_addr
- HDL params
ADDR_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
USER_WIDTH - default value 0 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 6bits> - MASTER
burst - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
cache - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
len - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
lock - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
size - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
qos - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
domain - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
region - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
snoop - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
bar - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
- class hwtLib.amba.ace.BAR[source]¶
Bases:
object
- BARRIER = 1¶
- IGNORE = 2¶
- NORMAL = 0¶
- SYNCHRONIZATION = 3¶
- class hwtLib.amba.ace.CACHE[source]¶
Bases:
object
- DEVICE = 0¶
- NON_CACHEABLE = 3¶
- WRITE_BACK = 11¶
- WRITE_THROUGH = 7¶
hwtLib.amba.aceLite module¶
- class hwtLib.amba.aceLite.AceLite(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi4Lite
AMBA ACE-lite interface
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
ar - of type hwtLib.amba.aceLite.AceLite_addr - MASTER
r - of type hwtLib.amba.axi4Lite.Axi4Lite_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.aceLite.AceLite_addr - MASTER
w - of type hwtLib.amba.axi4Lite.Axi4Lite_w - MASTER
b - of type hwtLib.amba.axi4Lite.Axi4Lite_b - SLAVE (Master=IN)
- AR_CLS¶
alias of
AceLite_addr
- AW_CLS¶
alias of
AceLite_addr
- class hwtLib.amba.aceLite.AceLite_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi4Lite_addr
- HDL params
ADDR_WIDTH - default value 32 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
domain - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
snoop - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
bar - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
hwtLib.amba.axi3 module¶
- class hwtLib.amba.axi3.Axi3(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite
AMBA Axi3 bus interface
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
- HDL IO
ar - of type hwtLib.amba.axi3.Axi3_addr - MASTER
r - of type hwtLib.amba.axi3.Axi3_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.axi3.Axi3_addr - MASTER
w - of type hwtLib.amba.axi3.Axi3_w - MASTER
b - of type hwtLib.amba.axi3.Axi3_b - SLAVE (Master=IN)
- LEN_WIDTH = 4¶
- LOCK_WIDTH = 2¶
- class hwtLib.amba.axi3.Axi3_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_addr
,Axi_id
Axi3 address channel interface
- HDL params
ADDR_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
USER_WIDTH - default value 0 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 6bits> - MASTER
burst - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
cache - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
len - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
lock - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
size - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
- LEN_WIDTH = 4¶
- LOCK_WIDTH = 2¶
- class hwtLib.amba.axi3.Axi3_addrAgent(sim: HdlSimulator, intf: Axi3_addr, allowNoReset=False)[source]¶
Bases:
AxiStreamAgent
Simulation agent for
Axi3_addr
interfaceinput/output data stored in list under “data” property data contains tuples (id, addr, burst, cache, len, lock, prot, size, qos, optionally user)
- class hwtLib.amba.axi3.Axi3_b(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_b
,Axi_id
Axi3 write response channel interface
- HDL params
ID_WIDTH - default value 0 of type int
- HDL IO
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3.Axi3_bAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
Simulation agent for
Axi3_b
interfaceinput/output data stored in list under “data” property data contains tuples (id, resp)
- class hwtLib.amba.axi3.Axi3_r(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_r
,Axi_id
Axi 3 read channel interface
- HDL params
ID_WIDTH - default value 6 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 6bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3.Axi3_rAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
Simulation agent for
Axi4_r
interfaceinput/output data stored in list under “data” property data contains tuples (id, data, resp, last)
- class hwtLib.amba.axi3.Axi3_w(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
-
Axi3 write channel interface (simplified AxiStream)
- HDL params
ID_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
strb - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
hwtLib.amba.axi3Lite module¶
- class hwtLib.amba.axi3Lite.Axi3Lite(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
AMBA AXI3-lite interface
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
ar - of type hwtLib.amba.axi3Lite.Axi3Lite_addr - MASTER
r - of type hwtLib.amba.axi3Lite.Axi3Lite_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.axi3Lite.Axi3Lite_addr - MASTER
w - of type hwtLib.amba.axi3Lite.Axi3Lite_w - MASTER
b - of type hwtLib.amba.axi3Lite.Axi3Lite_b - SLAVE (Master=IN)
- AR_CLS¶
alias of
Axi3Lite_addr
- AW_CLS¶
alias of
Axi3Lite_addr
- B_CLS¶
alias of
Axi3Lite_b
- LEN_WIDTH = 0¶
- R_CLS¶
alias of
Axi3Lite_r
- W_CLS¶
alias of
Axi3Lite_w
- class hwtLib.amba.axi3Lite.Axi3LiteAgent(sim: HdlSimulator, intf)[source]¶
Bases:
AgentBase
Composite simulation agent with agent for every axi channel change of enable is propagated to each child
data for each agent is stored in agent for given channel (ar, aw, r, … property)
- class hwtLib.amba.axi3Lite.Axi3Lite_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL params
ADDR_WIDTH - default value 32 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3Lite.Axi3Lite_addrAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
- Variables
~.data – iterable of addr
- class hwtLib.amba.axi3Lite.Axi3Lite_b(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL IO
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3Lite.Axi3Lite_bAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
- Variables
~.data – iterable of resp
- class hwtLib.amba.axi3Lite.Axi3Lite_r(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3Lite.Axi3Lite_w(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
strb - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi3Lite.Axi3Lite_wAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
- Variables
~.data – iterable of tuples (data, strb)
- class hwtLib.amba.axi3Lite.AxiLite_rAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
- Variables
~.data – iterable of tuples (data, resp)
- class hwtLib.amba.axi3Lite.IP_Axi3Lite[source]¶
Bases:
IntfIpMeta
- asQuartusTcl(buff: List[str], version: str, component: Component, packager: IpPackager, thisIf: Interface)[source]¶
Add interface to Quartus tcl
- Parameters
buff – line buffer for output
version – Quartus version
intfName – name of top interface
component – component object from ipcore generator
packager – instance of IpPackager which is packagin current design
allInterfaces – list of all interfaces of top unit
thisIf – interface to add into Quartus TCL
- library¶
- name¶
- postProcess(component: Component, packager: IpPackager, thisIf: Axi3Lite)[source]¶
- vendor¶
- version¶
hwtLib.amba.axi4 module¶
- class hwtLib.amba.axi4.Axi4(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3
AMBA AXI4 bus interface https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- Variables
~.ar – read address channel
~.r – read data channel
~.aw – write address channel
~.w – write data channel
~.b – write acknowledge channel
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
- HDL IO
ar - of type hwtLib.amba.axi4.Axi4_addr - MASTER
r - of type hwtLib.amba.axi4.Axi4_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.axi4.Axi4_addr - MASTER
w - of type hwtLib.amba.axi4.Axi4_w - MASTER
b - of type hwtLib.amba.axi4.Axi4_b - SLAVE (Master=IN)
- LEN_WIDTH = 8¶
- LOCK_WIDTH = 1¶
- _ag: Optional[AgentBase]¶
- _associatedClk: Optional[Interface]¶
- _associatedRst: Optional[Interface]¶
- _ctx: Optional[RtlNetlist]¶
- _direction: INTF_DIRECTION¶
- _hdl_port: Optional[HdlPortItem]¶
- _masterDir: DIRECTION¶
- _name: Optional[str]¶
- _parent: Optional['Unit']¶
- _setAttrListener: Optional[Callable[[str, object], None]]¶
- class hwtLib.amba.axi4.Axi4_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3_addr
Axi4 address channel interface (axi3 address channel with different size of len and lock signals and additional qos signal)
- HDL params
ADDR_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
USER_WIDTH - default value 0 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 6bits> - MASTER
burst - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
cache - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
len - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
lock - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
size - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
qos - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
- LEN_WIDTH = 8¶
- LOCK_WIDTH = 1¶
- _ag: Optional[AgentBase]¶
- _associatedClk: Optional[Interface]¶
- _associatedRst: Optional[Interface]¶
- _ctx: Optional[RtlNetlist]¶
- _direction: INTF_DIRECTION¶
- _hdl_port: Optional[HdlPortItem]¶
- _masterDir: DIRECTION¶
- _name: Optional[str]¶
- _parent: Optional['Unit']¶
- _setAttrListener: Optional[Callable[[str, object], None]]¶
- class hwtLib.amba.axi4.Axi4_addrAgent(sim: HdlSimulator, intf: Axi3_addr, allowNoReset=False)[source]¶
Bases:
AxiStreamAgent
- class hwtLib.amba.axi4.Axi4_b(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3_b
Axi4 write response channel interface (same as
Axi3_b
)- HDL params
ID_WIDTH - default value 0 of type int
- HDL IO
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi4.Axi4_r(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3_r
Axi4 read channel interface (same as r
Axi3_r
)- HDL params
ID_WIDTH - default value 6 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 6bits> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi4.Axi4_w(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
-
Axi4 write channel interface (
Axi3_w
without id signal)- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
strb - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
hwtLib.amba.axi4Lite module¶
- class hwtLib.amba.axi4Lite.Axi4Lite(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite
Axi4-lite bus interface (Same as
Axi3Lite
just address channels do have “prot” signal)- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
ar - of type hwtLib.amba.axi4Lite.Axi4Lite_addr - MASTER
r - of type hwtLib.amba.axi4Lite.Axi4Lite_r - SLAVE (Master=IN)
aw - of type hwtLib.amba.axi4Lite.Axi4Lite_addr - MASTER
w - of type hwtLib.amba.axi4Lite.Axi4Lite_w - MASTER
b - of type hwtLib.amba.axi4Lite.Axi4Lite_b - SLAVE (Master=IN)
- AR_CLS¶
alias of
Axi4Lite_addr
- AW_CLS¶
alias of
Axi4Lite_addr
- B_CLS¶
alias of
Axi4Lite_b
- R_CLS¶
alias of
Axi4Lite_r
- W_CLS¶
alias of
Axi4Lite_w
- _ag: Optional[AgentBase]¶
- _associatedClk: Optional[Interface]¶
- _associatedRst: Optional[Interface]¶
- _ctx: Optional[RtlNetlist]¶
- _direction: INTF_DIRECTION¶
- _hdl_port: Optional[HdlPortItem]¶
- _masterDir: DIRECTION¶
- _name: Optional[str]¶
- _parent: Optional['Unit']¶
- _setAttrListener: Optional[Callable[[str, object], None]]¶
- class hwtLib.amba.axi4Lite.Axi4Lite_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_addr
Axi3Lite_addr
with “prot” signal added.- HDL params
ADDR_WIDTH - default value 32 of type int
- HDL IO
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
prot - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
- class hwtLib.amba.axi4Lite.Axi4Lite_addrAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
Axi3Lite_addrAgent
- Variables
~.data – iterable of addr
- class hwtLib.amba.axi4Lite.Axi4Lite_b(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_b
(Same as
Axi3Lite_b
)- HDL IO
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi4Lite.Axi4Lite_r(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_r
(Same as
Axi3Lite_r
)- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
resp - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi4Lite.Axi4Lite_w(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi3Lite_w
(Same as
Axi3Lite_w
)- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
strb - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
hwtLib.amba.axi_intf_common module¶
- class hwtLib.amba.axi_intf_common.Axi_hs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
AXI handshake interface with ready and valid signal (same as HandshakeSync just vld is valid and rd is ready) transaction happens when both ready and valid are high
- Variables
~.ready – when high slave is ready to receive data
~.valid – when high master is sending data to slave
- HDL IO
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axi_intf_common.Axi_id(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
- HDL params
ID_WIDTH - default value 0 of type int
- class hwtLib.amba.axi_intf_common.Axi_strb(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
strb - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
hwtLib.amba.axis module¶
- class hwtLib.amba.axis.AxiStream(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Axi_hs
,Axi_id
,Axi_user
,Axi_strb
AMBA AXI-stream interface https://static.docs.arm.com/ihi0051/a/IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf
- Variables
~.IS_BIGENDIAN – Param which specifies if interface uses bigendian byte order or little-endian byte order
~.DATA_WIDTH – Param which specifies width of data signal
~.HAS_STRB – if set strb signal is present
~.HAS_KEEP – if set keep signal is present
~.ID_WIDTH – if > 0 id signal is present and this is it’s width
~.DEST_WIDTH – if > 0 dest signal is present and this is it’s width
~.id – optional signal wich specifies id of transaction
~.dest – optional signal which specifies destination of transaction
~.data – main data signal
~.keep – optional signal which signalize which bytes should be keept and which should be discarded
~.strb – optional signal which signalize which bytes are valid
~.last – signal which if high this data is last in this frame
~.user – optional signal which can be used for arbitrary purposes
- HDL params
IS_BIGENDIAN - default value False of type bool
USE_STRB - default value False of type bool
USE_KEEP - default value False of type bool
ID_WIDTH - default value 0 of type int
DEST_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
USER_WIDTH - default value 0 of type int
- HDL IO
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
ready - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
valid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.amba.axis.AxiStreamAgent(sim: HdlSimulator, intf: AxiStream, allowNoReset=False)[source]¶
Bases:
BaseAxiAgent
,UniversalHandshakedAgent
Simulation agent for
AxiStream
interfaceinput/output data stored in list under “data” property data contains tuples
Format of data tules is derived from signals on AxiStream interface Order of values coresponds to definition of interface signals. If all signals are present fotmat of tuple will be (id, dest, data, strb, keep, user, last)
- class hwtLib.amba.axis.IP_AXIStream[source]¶
Bases:
IntfIpMeta
Class which specifies how to describe AxiStream interfaces in IP-core
- library¶
- name¶
- vendor¶
- version¶
- hwtLib.amba.axis._axis_recieve_bytes(ag_data: Deque[Union[Tuple[BitsVal, BitsVal, BitsVal, BitsVal], Tuple[BitsVal, BitsVal, BitsVal], Tuple[BitsVal, BitsVal]]], D_B: int, use_keep: bool, use_id: bool) Tuple[int, List[int]] [source]¶
- Parameters
ag_data – list of axi stream words, number of item in tuple depends on use_keep and use_id
use_keep – specifies if input tuples contain keep mask
use_id – specifies if input tuples contain axi stream id
D_B – number of bytes in word
- hwtLib.amba.axis._axis_send_bytes(axis: AxiStream, data_B: List[int], withStrb: bool, offset: int) List[Tuple[int, int, int]] [source]¶
- hwtLib.amba.axis.axis_recieve_bytes(axis: AxiStream) Tuple[int, List[int]] [source]¶
Read data from AXI Stream agent in simulation and use keep signal to mask out unused bytes
- hwtLib.amba.axis.axis_send_bytes(axis: AxiStream, data_B: Union[List[int], bytes], offset=0) None [source]¶
- Parameters
axis – AxiStream master which is driver from the simulation
data_B – bytes to send
offset – number of empty bytes which should be added before data in frame (and use keep signal to mark such a bytes)
hwtLib.amba.axis_fullduplex module¶
- class hwtLib.amba.axis_fullduplex.AxiStreamFullDuplex(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
- HDL params
IS_BIGENDIAN - default value False of type bool
USE_STRB - default value False of type bool
USE_KEEP - default value False of type bool
ID_WIDTH - default value 0 of type int
DEST_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
USER_WIDTH - default value 0 of type int
HAS_RX - default value True of type bool
HAS_TX - default value True of type bool
- HDL IO
tx - of type hwtLib.amba.axis.AxiStream - MASTER
rx - of type hwtLib.amba.axis.AxiStream - SLAVE (Master=IN)
- class hwtLib.amba.axis_fullduplex.AxiStreamFullDuplexAgent(sim: HdlSimulator, intf: AxiStreamFullDuplex)[source]¶
Bases:
AgentBase
- __init__(sim: HdlSimulator, intf: AxiStreamFullDuplex)[source]¶
hwtLib.amba.constants module¶
Constant used for a signals in AXI, AXI-lite interfaces.
https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf
- hwtLib.amba.constants.CACHE_DEFAULT = 3¶
ARCACHE[3:0]
AWCACHE[3:0]
Memory type
0000
0000
Device Non-bufferable
0001
0001
Device Bufferable
0010
0010
Normal Non-cacheable Non-bufferable
0011
0011
Normal Non-cacheable Bufferable
1010
0110
Write-through No-allocate
1110 (0110)
0110
Write-through Read-allocate
1010
1110 (1010)
Write-through Write-allocate
1110
1110
Write-through Read and Write-allocate
1011
0111
Write-back No-allocate
1111 (0111)
0111
Write-back Read-allocate
1011
1111 (1011)
Write-back Write-allocate
1111
1111
Write-back Read and Write-allocate
- hwtLib.amba.constants.LOCK_DEFAULT = 0¶
RESP
Response
Description
0b00
OKAY
Normal access success
0b01
EXOKAY
Exclusive access success
0b10
SLVERR
Slave error
0b11
DECERR
Decode error
- hwtLib.amba.constants.PROT_DEFAULT = 0¶
- Note
“prot” is an access permissions signals that can be used to protect against illegal transactions.
PROT
Value
Function
[0]
0
Unprivileged access
1
Privileged access
[1]
0
Secure access
1
Non-secure access
[2]
0
Data access
1
Instruction access