hwtLib.amba package

This package is dedicated to component and utilities related to ARM AMBA interfaces.

This icludes:

  • AMBA AXI3

  • AMBA AXI3-lite

  • AMBA AXI4

  • AMBA AXI4-lite

  • AMBA AXI4-stream

  • AMBA ACE

  • and others

Available specifications:

Subpackages

Submodules

hwtLib.amba.ace module

class hwtLib.amba.ace.AR_MODE[source]

Bases: object

class BARRIER[source]

Bases: object

INNER = (1, 1, 0)
NON = (1, 0, 0)
OUTER = (1, 2, 0)
SYSTEM = (1, 3, 0)
class CACHE_MAINTENANCE[source]

Bases: object

class CLEAN_INVALID[source]

Bases: object

INNER = (0, 1, 9)
NON = (0, 0, 9)
OUTER = (0, 2, 9)
class CLEAN_SHARED[source]

Bases: object

INNER = (0, 1, 8)
NON = (0, 0, 8)
OUTER = (0, 2, 8)
class MAKE_INVALID[source]

Bases: object

INNER = (0, 1, 13)
NON = (0, 0, 13)
OUTER = (0, 2, 13)
class COHERENT[source]

Bases: object

class CLEAN_UNIQUE[source]

Bases: object

INNER = (0, 1, 11)
OUTER = (0, 2, 11)
class MAKE_UNIQUE[source]

Bases: object

INNER = (0, 1, 12)
OUTER = (0, 2, 12)
class READ_CLEAN[source]

Bases: object

INNER = (0, 1, 2)
OUTER = (0, 2, 2)
class READ_NOT_SHARED_DIRTY[source]

Bases: object

INNER = (0, 1, 3)
OUTER = (0, 2, 3)
class READ_ONCE[source]

Bases: object

INNER = (0, 1, 0)
OUTER = (0, 2, 0)
class READ_SHARED[source]

Bases: object

INNER = (0, 1, 1)
OUTER = (0, 2, 1)
class READ_UNIQUE[source]

Bases: object

INNER = (0, 1, 7)
OUTER = (0, 2, 7)
class DVM[source]

Bases: object

class COMPLETE[source]

Bases: object

INNER = (0, 1, 14)
OUTER = (0, 2, 14)
class MESSAGE[source]

Bases: object

INNER = (0, 2, 15)
OUTER = (0, 2, 15)
class NO_SNOOP[source]

Bases: object

class READ[source]

Bases: object

NON = (0, 0, 0)
SYSTEM = (0, 3, 0)
class hwtLib.amba.ace.Ace(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi4

https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • SNOOP_ADDR_WIDTH - default value 32 of type int

  • SNOOP_DATA_WIDTH - default value 32 of type int

HDL IO:
AR_CLS

alias of Ace_addr

AW_CLS

alias of Ace_addr

__annotations__ = {}
_getIpCoreIntfClass()[source]
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.ace.AceSnoop_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL params:

  • SNOOP_ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • snoop - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.ace.AceSnoop_data(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL params:

  • SNOOP_DATA_WIDTH - default value 32 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.ace.AceSnoop_resp(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL IO:

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.ace.Ace_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi4_addr

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • ID_WIDTH - default value 6 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 6bits> - UNKNOWN

  • burst - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • cache - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • len - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • lock - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit, force_vector> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • qos - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • domain - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • region - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • snoop - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • bar - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.ace.BAR[source]

Bases: object

BARRIER = 1
IGNORE = 2
NORMAL = 0
SYNCHRONIZATION = 3
class hwtLib.amba.ace.CACHE[source]

Bases: object

DEVICE = 0
NON_CACHEABLE = 3
WRITE_BACK = 11
WRITE_THROUGH = 7
class hwtLib.amba.ace.DOMAIN[source]

Bases: object

INNER_SHARABLE = 1
NON_SHARABLE = 0
OUTER_SHARABLE = 2
SYSTEM = 3
hwtLib.amba.ace.setAceArMode(arbar, ardomain, arsnoop, transactionType)[source]

hwtLib.amba.aceLite module

class hwtLib.amba.aceLite.AceLite(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi4Lite

AMBA ACE-lite interface

https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:
AR_CLS

alias of AceLite_addr

AW_CLS

alias of AceLite_addr

__annotations__ = {}
_getIpCoreIntfClass()[source]
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.aceLite.AceLite_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi4Lite_addr

HDL params:

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • domain - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • snoop - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • bar - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]

hwtLib.amba.axi3 module

class hwtLib.amba.axi3.Axi3(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite

AMBA Axi3 bus interface

https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO:
AR_CLS

alias of Axi3_addr

AW_CLS

alias of Axi3_addr

B_CLS

alias of Axi3_b

LEN_WIDTH = 4
LOCK_WIDTH = 2
R_CLS

alias of Axi3_r

W_CLS

alias of Axi3_w

__annotations__ = {}
_getIpCoreIntfClass()[source]
class hwtLib.amba.axi3.Axi3_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_addr, Axi_id

Axi3 address channel interface

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • ID_WIDTH - default value 6 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 6bits> - UNKNOWN

  • burst - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • cache - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • len - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • lock - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

LEN_WIDTH = 4
LOCK_WIDTH = 2
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3.Axi3_addrAgent(sim: HdlSimulator, hwIO: Axi3_addr, allowNoReset=False)[source]

Bases: Axi4StreamAgent

Simulation agent for Axi3_addr interface

input/output data stored in list under “data” property data contains tuples (id, addr, burst, cache, len, lock, prot, size, qos, optionally user)

__init__(sim: HdlSimulator, hwIO: Axi3_addr, allowNoReset=False)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

create_addr_req(addr, _len, _id=0, burst=1, cache=3, lock=0, prot=0, size=<object object>, user=None, DATA_WIDTH: int | None = None)[source]

Create a default AXI address transaction :note: transaction is created and returned but it is not added to a agent data

class hwtLib.amba.axi3.Axi3_b(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_b, Axi_id

Axi3 write response channel interface

HDL params:

  • ID_WIDTH - default value 0 of type int

HDL IO:

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3.Axi3_bAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Simulation agent for Axi3_b interface

input/output data stored in list under “data” property data contains tuples (id, resp)

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3.Axi3_r(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_r, Axi_id

Axi 3 read channel interface

HDL params:

  • ID_WIDTH - default value 6 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 6bits> - UNKNOWN

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3.Axi3_rAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Simulation agent for Axi4_r interface

input/output data stored in list under “data” property data contains tuples (id, data, resp, last)

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3.Axi3_w(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs, Axi_strb

Axi3 write channel interface (simplified Axi4Stream)

HDL params:

  • ID_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • strb - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3.IP_Axi3[source]

Bases: IP_Axi3Lite

IP core interface meta for Axi3 interface

__init__()[source]
library
name
postProcess(component: Component, packager: IpPackager, thisIf: Axi3)[source]
vendor
version

hwtLib.amba.axi3Lite module

class hwtLib.amba.axi3Lite.Axi3Lite(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

AMBA AXI3-lite interface

https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:
AR_CLS

alias of Axi3Lite_addr

AW_CLS

alias of Axi3Lite_addr

B_CLS

alias of Axi3Lite_b

LEN_WIDTH = 0
R_CLS

alias of Axi3Lite_r

W_CLS

alias of Axi3Lite_w

__annotations__ = {}
_getAddrStep()[source]
Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getIpCoreIntfClass()[source]
_getWordAddrStep()[source]
Returns:

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3Lite.Axi3LiteAgent(sim: HdlSimulator, hwIO)[source]

Bases: AgentBase

Composite simulation agent with agent for every axi channel change of enable is propagated to each child

data for each agent is stored in agent for given channel (ar, aw, r, … property)

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO)[source]
create_addr_req(*args, **kwargs)[source]
getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getEnable()[source]
getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

setEnable(en)[source]
Note:

If IO should be disabled in simulation you still likely want to perform reset of IO so you do not want to disable agent before simulation.

class hwtLib.amba.axi3Lite.Axi3Lite_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL params:

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3Lite.Axi3Lite_addrAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Variables:

~.data – iterable of addr

__annotations__ = {}
create_addr_req(addr, prot=None)[source]
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3Lite.Axi3Lite_b(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL IO:

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3Lite.Axi3Lite_bAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Variables:

~.data – iterable of resp

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3Lite.Axi3Lite_r(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3Lite.Axi3Lite_w(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • strb - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi3Lite.Axi3Lite_wAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Variables:

~.data – iterable of tuples (data, strb)

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3Lite.AxiLite_rAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: BaseAxiAgent

Variables:

~.data – iterable of tuples (data, resp)

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi3Lite.IP_Axi3Lite[source]

Bases: IntfIpMeta

__annotations__ = {}
__init__()[source]
_toLowerCase(d)[source]
asQuartusTcl(buff: List[str], version: str, component: Component, packager: IpPackager, thisIf: HwIO)[source]

Add interface to Quartus tcl

Parameters:

  • buff – line buffer for output

  • version – Quartus version

  • intfName – name of top interface

  • component – component object from ipcore generator

  • packager – instance of IpPackager which is packaging current design

  • allInterfaces – list of all interfaces of top unit

  • thisIf – interface to add into Quartus TCL

get_quartus_map()[source]
library
name
postProcess(component: Component, packager: IpPackager, thisIf: Axi3Lite)[source]
vendor
version

hwtLib.amba.axi4 module

class hwtLib.amba.axi4.Axi4(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3

AMBA AXI4 bus interface https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

Variables:

  • ~.ar – read address channel

  • ~.r – read data channel

  • ~.aw – write address channel

  • ~.w – write data channel

  • ~.b – write acknowledge channel

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO:
AR_CLS

alias of Axi4_addr

AW_CLS

alias of Axi4_addr

B_CLS

alias of Axi4_b

LEN_WIDTH = 8
LOCK_WIDTH = 1
R_CLS

alias of Axi4_r

W_CLS

alias of Axi4_w

__annotations__ = {}
_getIpCoreIntfClass()[source]
class hwtLib.amba.axi4.Axi4_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3_addr

Axi4 address channel interface (axi3 address channel with different size of len and lock signals and additional qos signal)

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • ID_WIDTH - default value 6 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 6bits> - UNKNOWN

  • burst - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • cache - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • len - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • lock - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit, force_vector> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • qos - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

LEN_WIDTH = 8
LOCK_WIDTH = 1
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi4.Axi4_addrAgent(sim: HdlSimulator, hwIO: Axi3_addr, allowNoReset=False)[source]

Bases: Axi4StreamAgent

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: Axi3_addr, allowNoReset=False)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

create_addr_req(addr, _len, _id=0, burst=1, cache=3, lock=0, prot=0, size=<object object>, qos=0, user=None, DATA_WIDTH: int | None = None)[source]

Create a default AXI address transaction :note: transaction is created and returned but it is not added to a agent data

class hwtLib.amba.axi4.Axi4_b(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3_b

Axi4 write response channel interface (same as Axi3_b)

HDL params:

  • ID_WIDTH - default value 0 of type int

HDL IO:

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi4.Axi4_r(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3_r

Axi4 read channel interface (same as r Axi3_r)

HDL params:

  • ID_WIDTH - default value 6 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 6bits> - UNKNOWN

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi4.Axi4_w(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs, Axi_strb

Axi4 write channel interface (Axi3_w without id signal)

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • strb - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi4.IP_Axi4[source]

Bases: IP_Axi3

IP core interface meta for Axi4 interface

__annotations__ = {}
__init__()[source]
library
name
vendor
version

hwtLib.amba.axi4Lite module

class hwtLib.amba.axi4Lite.Axi4Lite(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite

Axi4-lite bus interface (Same as Axi3Lite just address channels do have “prot” signal)

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:
AR_CLS

alias of Axi4Lite_addr

AW_CLS

alias of Axi4Lite_addr

B_CLS

alias of Axi4Lite_b

R_CLS

alias of Axi4Lite_r

W_CLS

alias of Axi4Lite_w

__annotations__ = {}
_getIpCoreIntfClass()[source]
class hwtLib.amba.axi4Lite.Axi4Lite_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_addr

Axi3Lite_addr with “prot” signal added.

HDL params:

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • prot - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi4Lite.Axi4Lite_addrAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: Axi3Lite_addrAgent

Variables:

~.data – iterable of addr

__annotations__ = {}
create_addr_req(addr, prot=0)[source]
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi4Lite.Axi4Lite_b(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_b

(Same as Axi3Lite_b)

HDL IO:

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi4Lite.Axi4Lite_r(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_r

(Same as Axi3Lite_r)

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • resp - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi4Lite.Axi4Lite_w(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi3Lite_w

(Same as Axi3Lite_w)

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • strb - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi4Lite.IP_Axi4Lite[source]

Bases: IP_Axi3Lite

IP core meta description for Axi4-lite interface

__annotations__ = {}
__init__()[source]
library
name
vendor
version

hwtLib.amba.axi4SSegmented module

class hwtLib.amba.axi4SSegmented.Axi4StreamSegmented(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs, Axi_user

Xilinx/AMD Segmented Axi4Stream interface used for 100G+ Ethernet https://docs.amd.com/r/1.3-English/pg314-versal-mrmac/Segmented-Mode?tocId=bPOyhICzaCLnbaKgrT0K4g

Variables:

  • ~.SEGMENT_CNT – number of segments of the bus

  • ~.SEGMENT_DATA_WIDTH – width of 1 segment of data signal

  • ~.ERROR_WIDTH – width of 1 segment of “err” signal (can be 0)

  • ~.SUPPORT_ZLP – if True “empty” signal 1b is wider and Zero Length Packets are supported

  • ~.USE_SOF – if True sof is present in user struct, sof + enable potentially allows for sparse streams (frame continuing in not directly consequent segment)

Typical configuration for Ethernet:

Ethernet DATA_WIDTH SEGMENT_CNT Frequency[MHz] ======== ========== =========== ============== 40G 128 1 312.5 [0] 50G 256 2 195.3125 [0] 100G 384 3 260.5 [0] 100G 512 1 390.625 [2] 400G 1024 8 390.625 [3] 600G 1536 12 390.625 [3]

[0] https://www.xilinx.com/content/dam/xilinx/publications/presentations/xilinx_network_security_offerings.pdf [1] https://www.intel.com/content/www/us/en/docs/programmable/773413.html [2] https://cdrdv2.intel.com/v1/dl/getContent/827074?fileName=ug20085-683100-827074.pdf [3] https://docs.amd.com/r/en-US/pg369-dcmac

HDL params:

  • SEGMENT_CNT - default value 4 of type int

  • SEGMENT_DATA_WIDTH - default value 64 of type int

  • BYTE_WIDTH - default value 8 of type int

  • SUPPORT_ZLP - default value False of type bool

  • USE_SOF - default value False of type bool

  • ERROR_WIDTH - default value 0 of type int

  • PACK_SEGMENT_BITS - default value False of type bool

HDL IO:

  • data - of type hwt.hwIOs.hwIOArray.HwIOArray - UNKNOWN

  • user - of type hwt.hwIOs.hwIOArray.HwIOArray - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
static _getWidthOfEmpty(SEGMENT_DATA_WIDTH: int, BYTE_WIDTH: int, SUPPORT_ZLP: bool)[source]
static _hasEmpty(SEGMENT_DATA_WIDTH: int, BYTE_WIDTH: int, SUPPORT_ZLP: bool)[source]
static _hasEnable(SEGMENT_CNT: int)[source]
_initSimAgent(sim: HdlSimulator)[source]
classmethod getEffectiveThroughput(CLK_FREQ: float | int, SEGMENT_CNT: int, DATA_WIDTH: int, PACKET_WIDTH: int)[source]
classmethod getMinNumberOfSegments(BITRATE: float | int, DATA_WIDTH: int, CLK_FREQ: float, MIN_PACKET_WIDTH: int)[source]
Parameters:

MIN_PACKET_WIDTH – the width of most waistful packet, e.g. (64 + 1) * 8b for ethernet

static getWastedBandwidthPercent(SEGMENT_CNT: int, DATA_WIDTH: int, PACKET_WIDTH: int)[source]
resolveTypes()[source]
See:

Axi4StreamSegmentedMockSegmentTy Axi4StreamSegmentedMockSegmentUserTy

unpackSegment(segmentIndex: int, v=None) → tuple[HBitsRtlSignal | HBitsConst, Axi4StreamSegmentedMockSegmentUserTy][source]
class hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedAgent(sim: HdlSimulator, hwIO: Axi4StreamSegmented, allowNoReset=False)[source]

Bases: BaseAxiAgent, UniversalRdVldSyncAgent

Simulation agent for Axi4StreamSegmented interface

input/output data stored in list under “data” property data contains tuples

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: Axi4StreamSegmented, allowNoReset=False)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(dataWord: tuple[tuple[HBitsConst, HConst], ...])[source]
Parameters:

dataWord – tuple of segments

class hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentTy(data: HBitsRtlSignal | HBitsConst, user: Axi4StreamSegmentedMockSegmentUserTy)[source]

Bases: object

Mock type to keep python typed for dynamically generated HdlType for Axi4StreamSegmented segment

__annotations__ = {'data': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst')], 'user': <class 'hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentUserTy'>}
__dataclass_fields__ = {'data': Field(name='data',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst')],default=<dataclasses._MISSING_TYPE object>,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'user': Field(name='user',type=<class 'hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentUserTy'>,default=<dataclasses._MISSING_TYPE object>,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD)}
__dataclass_params__ = _DataclassParams(init=True,repr=True,eq=True,order=False,unsafe_hash=False,frozen=False,match_args=True,kw_only=False,slots=False,weakref_slot=False)
__eq__(other)

Return self==value.

__hash__ = None
__init__(data: HBitsRtlSignal | HBitsConst, user: Axi4StreamSegmentedMockSegmentUserTy) → None
__match_args__ = ('data', 'user')
__repr__()

Return repr(self).

data: HBitsRtlSignal | HBitsConst
user: Axi4StreamSegmentedMockSegmentUserTy
class hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentUserTy(enable: HBitsRtlSignal | HBitsConst | None = None, sof: HBitsRtlSignal | HBitsConst | None = None, eof: HBitsRtlSignal | HBitsConst | None = None, err: HBitsRtlSignal | HBitsConst | None = None, empty: HBitsRtlSignal | HBitsConst | None = None)[source]

Bases: object

Mock type to keep python typed for dynamically generated HdlType for Axi4StreamSegmented segment user :attention: in real HStructConst the property is never None, but instead it is not presetnt

__annotations__ = {'empty': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType], 'enable': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType], 'eof': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType], 'err': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType], 'sof': typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType]}
__dataclass_fields__ = {'empty': Field(name='empty',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType],default=None,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'enable': Field(name='enable',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType],default=None,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'eof': Field(name='eof',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType],default=None,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'err': Field(name='err',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType],default=None,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'sof': Field(name='sof',type=typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst'), NoneType],default=None,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD)}
__dataclass_params__ = _DataclassParams(init=True,repr=True,eq=True,order=False,unsafe_hash=False,frozen=False,match_args=True,kw_only=False,slots=False,weakref_slot=False)
__eq__(other)

Return self==value.

__hash__ = None
__init__(enable: HBitsRtlSignal | HBitsConst | None = None, sof: HBitsRtlSignal | HBitsConst | None = None, eof: HBitsRtlSignal | HBitsConst | None = None, err: HBitsRtlSignal | HBitsConst | None = None, empty: HBitsRtlSignal | HBitsConst | None = None) → None
__match_args__ = ('enable', 'sof', 'eof', 'err', 'empty')
__repr__()

Return repr(self).

empty: HBitsRtlSignal | HBitsConst | None = None
enable: HBitsRtlSignal | HBitsConst | None = None
eof: HBitsRtlSignal | HBitsConst | None = None
err: HBitsRtlSignal | HBitsConst | None = None
sof: HBitsRtlSignal | HBitsConst | None = None
class hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockWordNoPackTy(data: list[HBitsRtlSignal | HBitsConst], user: list[Axi4StreamSegmentedMockSegmentUserTy])[source]

Bases: object

Mock type to keep python typed for dynamically generated HdlType for Axi4StreamSegmented segment

__annotations__ = {'data': list[typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst')]], 'user': list[hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentUserTy]}
__dataclass_fields__ = {'data': Field(name='data',type=list[typing.Union[ForwardRef('HBitsRtlSignal'), ForwardRef('HBitsConst')]],default=<dataclasses._MISSING_TYPE object>,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD), 'user': Field(name='user',type=list[hwtLib.amba.axi4SSegmented.Axi4StreamSegmentedMockSegmentUserTy],default=<dataclasses._MISSING_TYPE object>,default_factory=<dataclasses._MISSING_TYPE object>,init=True,repr=True,hash=None,compare=True,metadata=mappingproxy({}),kw_only=False,_field_type=_FIELD)}
__dataclass_params__ = _DataclassParams(init=True,repr=True,eq=True,order=False,unsafe_hash=False,frozen=False,match_args=True,kw_only=False,slots=False,weakref_slot=False)
__eq__(other)

Return self==value.

__hash__ = None
__init__(data: list[HBitsRtlSignal | HBitsConst], user: list[Axi4StreamSegmentedMockSegmentUserTy]) → None
__match_args__ = ('data', 'user')
__repr__()

Return repr(self).

data: list[HBitsRtlSignal | HBitsConst]
user: list[Axi4StreamSegmentedMockSegmentUserTy]
class hwtLib.amba.axi4SSegmented._Axi4StreamSegmentedWord(segmentWords: tuple[Deque[HBitsConst], Deque[HConst]], SEGMENT_CNT: int)[source]

Bases: object

Variables:

segmentWords – word of data and control signals encoded in user signal for a single segment

__init__(segmentWords: tuple[Deque[HBitsConst], Deque[HConst]], SEGMENT_CNT: int)[source]
empty()[source]
classmethod popSegmentWordFromAgentData(ag_data: Deque[tuple[HBitsConst, HConst]], SEGMENT_CNT: int) → Self[source]
popleft()[source]

hwtLib.amba.axi4SSegmentedSimFrameUtils module

class hwtLib.amba.axi4SSegmentedSimFrameUtils.Axi4StreamSegmentedFrameUtils(SEGMENT_DATA_WIDTH: int, SEGMENT_CNT: int, USER_SEGMENT_T: HStruct, BYTE_WIDTH: int = 8, SUPPORT_ZLP: bool = False, USE_SOF: bool = False, ERROR_WIDTH: int = 0, PACK_SEGMENT_BITS: bool = False)[source]

Bases: SimFrameUtils[tuple[tuple[HBitsConst, HConst], …]]

__annotations__ = {}
__init__(SEGMENT_DATA_WIDTH: int, SEGMENT_CNT: int, USER_SEGMENT_T: HStruct, BYTE_WIDTH: int = 8, SUPPORT_ZLP: bool = False, USE_SOF: bool = False, ERROR_WIDTH: int = 0, PACK_SEGMENT_BITS: bool = False)[source]
__orig_bases__ = (hwtLib.abstract.simFrameUtils.SimFrameUtils[tuple[tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.const.HConst], ...]],)
__parameters__ = ()
concatWordBits(frameBeats: Sequence[tuple[tuple[HBitsConst, HConst], ...]])[source]

Convert word tuple (produced by send_bytes() and pack_frame()) to flat HBitsConst (members of input tuple are typically ints so they need to be cast to correct type first)

classmethod from_HwIO(axiss: Axi4StreamSegmented) → Self[source]

Create a an instance of self configured for specified hwio instance

pack_frame(frameVal: HConst | Sequence[int]) → Generator[tuple[tuple[HBitsConst, HConst], ...], None, None][source]

pack data of structure into words on Axi4StreamSegmented interface

Parameters:

frameVal – value to be send, HConst instance or list of int for each byte

Returns:

generator of tuples tuples (data, USER_SEGMENT_T)

receive_bytes(ag_data: Deque[tuple[tuple[HBitsConst, HConst], ...]]) → tuple[int, list[int | HBitsConst], bool][source]
Parameters:

ag_data – list of axi stream segmented words, number of item in tuple depends on use_keep and use_id

Returns:

tuple (startSegmentIndex, data bytes, had error flag)

send_bytes(data_B: bytes | list[int], ag_data: Deque[tuple[tuple[HBitsConst, HConst], ...]], offset: int = 0) → list[tuple[tuple[HBitsConst, HConst], ...]][source]

Build frame out of data_B bytes and insert it into ag_data deque which is expected to be a queue of driver sim agent

hwtLib.amba.axi4s module

class hwtLib.amba.axi4s.Axi4Stream(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: Axi_hs, Axi_id, Axi_user, Axi_strb

AMBA AXI-stream interface https://static.docs.arm.com/ihi0051/a/IHI0051A_amba4_axi4_stream_v1_0_protocol_spec.pdf

Variables:

  • ~.IS_BIGENDIAN – HwParam which specifies if interface uses bigendian byte order or little-endian byte order

  • ~.DATA_WIDTH – HwParam which specifies width of data signal

  • ~.HAS_STRB – if set strb signal is present

  • ~.HAS_KEEP – if set keep signal is present

  • ~.ID_WIDTH – if > 0 id signal is present and this is it’s width

  • ~.DEST_WIDTH – if > 0 dest signal is present and this is it’s width

  • ~.id – optional signal wich specifies id of transaction

  • ~.dest – optional signal which specifies destination of transaction

  • ~.data – main data signal

  • ~.keep – optional signal which signalize which bytes should be keept and which should be discarded

  • ~.strb – optional signal which signalize which bytes are valid

  • ~.last – signal which if high this data is last in this frame

  • ~.user – optional signal which can be used for arbitrary purposes

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_getIpCoreIntfClass()[source]
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi4s.Axi4StreamAgent(sim: HdlSimulator, hwIO: Axi4Stream, allowNoReset=False)[source]

Bases: BaseAxiAgent, UniversalRdVldSyncAgent

Simulation agent for Axi4Stream interface

input/output data stored in list under “data” property data contains tuples

Format of data tuples is derived from signals on Axi4Stream interface Order of values corresponds to definition of interface signals. If all signals are present format of tuple will be (id, dest, data, strb, keep, user, last)

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: Axi4Stream, allowNoReset=False)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

class hwtLib.amba.axi4s.IP_AXI4Stream[source]

Bases: IntfIpMeta

Class which specifies how to describe Axi4Stream interfaces in IP-core

__annotations__ = {}
__init__()[source]
library
name
vendor
version

hwtLib.amba.axi4sSimFrameUtils module

class hwtLib.amba.axi4sSimFrameUtils.Axi4StreamSimFrameUtils(DATA_WIDTH: int, USE_STRB=False, USE_KEEP=False, USE_ID=False, BYTE_WIDTH=8)[source]

Bases: SimFrameUtils[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst]]

__annotations__ = {}
__init__(DATA_WIDTH: int, USE_STRB=False, USE_KEEP=False, USE_ID=False, BYTE_WIDTH=8)[source]
__orig_bases__ = (hwtLib.abstract.simFrameUtils.SimFrameUtils[typing.Union[tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst], tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst], tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst]]],)
__parameters__ = ()
concatWordBits(frameBeats: Sequence[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst]])[source]

Convert word tuple (produced by send_bytes() and pack_frame()) to flat HBitsConst (members of input tuple are typically ints so they need to be cast to correct type first)

classmethod from_HwIO(axis: Axi4Stream)[source]

Create a an instance of self configured for specified hwio instance

pack_frame(frameVal: HConst | Sequence[int]) → Generator[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst], None, None][source]

pack data of structure into words on axis interface Words are tuples (data, last) or (data, mask, last) depending on args.

Parameters:

frameVal – value to be send, HConst instance or list of int for each byte

Returns:

generator of tuples (data, strb, isLast), strb is omitted if withStrb=False

receive_bytes(ag_data: Deque[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst]]) → tuple[int, list[int]][source]
Parameters:

ag_data – list of axi stream words, number of item in tuple depends on use_keep and use_id

updackWordBits(v: HBitsConst)[source]

opposite of concatWordBits

hwtLib.amba.axi4sSimFrameUtils.axi4s_mask_propagate_best_effort(src: Axi4Stream, dst: Axi4Stream)[source]
hwtLib.amba.axi4sSimFrameUtils.axi4s_receive_bytes(axis: Axi4Stream) → tuple[int, list[int]][source]

Read data from AXI Stream agent in simulation and use keep signal to mask out unused bytes

hwtLib.amba.axi4sSimFrameUtils.axi4s_send_bytes(axis: Axi4Stream, data_B: list[int] | bytes, offset=0) → None[source]
Parameters:

  • axis – Axi4Stream master which is driver from the simulation

  • data_B – bytes to send

  • offset – number of empty bytes which should be added before data in frame (and use keep signal to mark such a bytes)

hwtLib.amba.axi4s_fullduplex module

class hwtLib.amba.axi4s_fullduplex.Axi4StreamFullDuplex(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • HAS_RX - default value True of type bool

  • HAS_TX - default value True of type bool

HDL IO:
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi4s_fullduplex.Axi4StreamFullDuplexAgent(sim: HdlSimulator, hwIO: Axi4StreamFullDuplex)[source]

Bases: AgentBase

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: Axi4StreamFullDuplex)[source]
getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

hwtLib.amba.axi_common module

hwtLib.amba.axi_common.AxiMap(prefix, listOfNames, d=None)[source]
class hwtLib.amba.axi_common.Axi_hs(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

AXI handshake interface with ready and valid signal (same as HwIORdVldSync just vld is valid and rd is ready) transaction happens when both ready and valid are high

Variables:

  • ~.ready – when high slave is ready to receive data

  • ~.valid – when high master is sending data to slave

HDL IO:

  • ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • valid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.amba.axi_common.Axi_id(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:

  • ID_WIDTH - default value 0 of type int

__annotations__ = {}
class hwtLib.amba.axi_common.Axi_strb(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • strb - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

__annotations__ = {}
class hwtLib.amba.axi_common.Axi_user(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

__annotations__ = {}

hwtLib.amba.constants module

Constant used for a signals in AXI, AXI-lite interfaces.

https://static.docs.arm.com/ihi0022/d/IHI0022D_amba_axi_protocol_spec.pdf

hwtLib.amba.constants.BYTES_IN_TRANS(n)[source]
hwtLib.amba.constants.CACHE_DEFAULT = 3

ARCACHE[3:0]

AWCACHE[3:0]

Memory type

0000

0000

Device Non-bufferable

0001

0001

Device Bufferable

0010

0010

Normal Non-cacheable Non-bufferable

0011

0011

Normal Non-cacheable Bufferable

1010

0110

Write-through No-allocate

1110 (0110)

0110

Write-through Read-allocate

1010

1110 (1010)

Write-through Write-allocate

1110

1110

Write-through Read and Write-allocate

1011

0111

Write-back No-allocate

1111 (0111)

0111

Write-back Read-allocate

1011

1111 (1011)

Write-back Write-allocate

1111

1111

Write-back Read and Write-allocate
hwtLib.amba.constants.LOCK_DEFAULT = 0

RESP

Response

Description

0b00

OKAY

Normal access success

0b01

EXOKAY

Exclusive access success

0b10

SLVERR

Slave error

0b11

DECERR

Decode error
hwtLib.amba.constants.PROT_DEFAULT = 0
Note:

“prot” is an access permissions signals that can be used to protect against illegal transactions.

PROT

Value

Function

[0]

0

Unprivileged access

1

Privileged access

[1]

0

Secure access

1

Non-secure access

[2]

0

Data access

1

Instruction access