Source code for hwtLib.amba.axi_comp.interconnect.base
from hwt.math import log2ceil
from hwt.synthesizer.unit import Unit
from hwtLib.handshaked.builder import HsBuilder
from hwtLib.handshaked.streamNode import StreamNode
from hwtLib.logic.oneHotToBin import oneHotToBin
[docs]def getSizeWidth(maxLen, dataWidth):
alignBits = log2ceil(dataWidth // 8 - 1)
lenBits = log2ceil(maxLen) + 1
return lenBits + alignBits
[docs]class AxiInterconnectBase(Unit):
"""
Abstract class for axi interconnects
"""
[docs] def getDpIntf(self, unit):
raise NotImplementedError("Implement this function in your implementation")
[docs] def connectDrivers(self, drivers, datapump):
"""
Connect drivers to datapump using this component
"""
for i, driver in enumerate(drivers):
# width of signals should be configured by the widest
# others drivers can have smaller widths of some signals for example id
self.drivers[i](self.getDpIntf(driver), fit=True)
datapump.driver(self.getDpIntf(self))
[docs] def reqHandler(self, dpReq, orderFifoIn):
# join with roundrobin on requests form drivers and selected index is stored into orderFifo
# because it is just proxy
driversReq = [d.req for d in self.drivers]
b = HsBuilder.join_fair(self, driversReq, exportSelected=True)
req = b.end
reqJoin = b.lastComp
StreamNode(masters=[req],
slaves=[dpReq, orderFifoIn]).sync()
dpReq(req, exclude=[dpReq.vld, dpReq.rd])
orderFifoIn.data(oneHotToBin(self, reqJoin.selectedOneHot.data))