hwtLib.amba.axi_comp.interconnect package

This package is dedicated to inteconnects for AXI interfaces.

Submodules

hwtLib.amba.axi_comp.interconnect.base module

class hwtLib.amba.axi_comp.interconnect.base.AxiInterconnectBase(hdlName: str | None = None)[source]

Bases: HwModule

Abstract class for axi interconnects

__annotations__ = {}
configureFromDrivers(drivers, datapump, byInterfaces=False)[source]

Check configuration of drivers and resolve MAX_LEN and aply it on datapump and this interconnect

connectDrivers(drivers, datapump)[source]

Connect drivers to datapump using this component

getDpHwIO(unit)[source]
reqHandler(dpReq, orderFifoIn)[source]
hwtLib.amba.axi_comp.interconnect.base.getSizeWidth(maxLen, dataWidth)[source]

hwtLib.amba.axi_comp.interconnect.common module

class hwtLib.amba.axi_comp.interconnect.common.AxiInterconnectCommon(hwIOCls, hdlName: str | None = None)[source]

Bases: BusInterconnect

__annotations__ = {}
__init__(hwIOCls, hdlName: str | None = None)[source]

hwtLib.amba.axi_comp.interconnect.matrix module

class hwtLib.amba.axi_comp.interconnect.matrix.AxiInterconnectMatrix(hwIOCls, hdlName: str | None = None)[source]

Bases: AxiInterconnectCommon

Matrix style interconnect for AXI-3/4/Lite interfaces

Variables:

  • ~.SLAVES – list of configuration of slave interfaces, configuration is tuple (address, size)

  • ~.MASTERS – list of configuration of master interfaces, configuration is ALL if the master has visibility to all slaves or tuple of flags, where True means the master has visibility to slave on this index

  • ~.AW_AND_W_WORD_TOGETHER – configures if supports AXI AW and W first word in a single clock cycle (if False the W first word must arrive after AW word)

HDL params:

  • SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple

  • MASTERS - default value ({(1, ‘RW’), (0, ‘READ’)},) of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • MAX_TRANS_OVERLAP - default value 16 of type int

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • AW_AND_W_WORD_TOGETHER - default value True of type bool

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
configure_sub_interconnect(master_indexes: Set[int], slave_indexes: Set[int], sub_interconnect: AxiInterconnectMatrixR | AxiInterconnectMatrixW) → List[Tuple[AxiInterconnectCommon, INTF_DIRECTION, int, int]][source]
Note:

sub interconnect are used if there are distinct group of masters and slaves in order to avoid unnecessary logic

Returns:

tuples (sub_interconnect, SLAVE/MASTER, index of interface on this component, index of interface on sub_interconnect)

hwtLib.amba.axi_comp.interconnect.matrix.example_AxiInterconnectMatrix()[source]

hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar module

class hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar.AxiInterconnectMatrixAddrCrossbar(axi_addr_cls)[source]

Bases: HwModule

Component which implements N to M crossbar for AXI address channel. If there are multiple masters connected to any slave the access is mannaged by round-robin.

Variables:

  • ~.order_s_index_for_m_data_out – handshaked interface with index of slave for each master, data is send on start of the transaction

  • ~.order_m_index_for_s_data_out – handshaked interface with index of master for each slave, data is send on start of the transaction

HDL params:

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4.Axi4_addr’> of type type

  • SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple

  • MASTERS - default value ({0, 1}, {0, 1}) of type tuple

  • ADDR_WIDTH - default value 32 of type int

  • ID_WIDTH - default value 6 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

  • order_m_index_for_s_data_out - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

  • order_s_index_for_m_data_out - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
__init__(axi_addr_cls)[source]
addr_handler_N_to_M(master_addr_channels, slave_addr_channels, order_m_index_for_s_data_in, order_s_index_for_m_data_in)[source]

for each slave use roundrobin to select the master and store indexes of master and slave for later use

addr_handler_build_addr_mux(slv_addr_tmp, master_addr_channels, addr_assignments, isSelectedFlags)[source]

build all master addr to this slave mux

static priorityAck(priorityReg, vldSignals, index)[source]
propagate_addr(master_addr_channels, slave_addr_channels) → List[List[Tuple[RtlSignal, HdlAssignmentContainer]]][source]
Returns:

matrix of tuple(addr select, addr assignment) for all masters and slaves (master X slave)

hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar.example_AxiInterconnectMatrixAddrCrossbar()[source]

hwtLib.amba.axi_comp.interconnect.matrixCrossbar module

class hwtLib.amba.axi_comp.interconnect.matrixCrossbar.AxiInterconnectMatrixCrossbar(hwIOCls, hdlName: str | None = None)[source]

Bases: HwModule

Crossbar for AXI-Stream like interfaces where internal switch box can be driven by

HDL params:

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4.Axi4_r’> of type type

  • INPUT_CNT - default value 2 of type int

  • OUTPUTS - default value [{0, 1}, {0, 1}] of type list

  • ID_WIDTH - default value 6 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

  • order_dout_index_for_din_in - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • order_din_index_for_dout_in - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

schematic
__annotations__ = {}
__init__(hwIOCls, hdlName: str | None = None)[source]
static _masters_for_slave(masters, slave_cnt) → Dict[int, Set[int]][source]
connection_handler_N_to_M(dataOut_channels, dataIn_channels, order_dout_index_for_din, order_din_index_for_dout)[source]
get_last(hwIO: HwIO)[source]
handler_data_mux(dataOut_channels, dataIn_channels, order_din_index_for_dout)[source]
handler_din_rd(dataOut_channels, dataIn_channels, order_dout_index_for_din, order_din_index_for_dout)[source]
handler_dout_vld(dataOut_channels, dataIn_channels, order_dout_index_for_din, order_din_index_for_dout)[source]
hwtLib.amba.axi_comp.interconnect.matrixCrossbar.example_AxiInterconnectMatrixCrossbar()[source]

hwtLib.amba.axi_comp.interconnect.matrixR module

class hwtLib.amba.axi_comp.interconnect.matrixR.AxiInterconnectMatrixR(hwIOCls, hdlName: str | None = None)[source]

Bases: AxiInterconnectCommon

Read only AXI3/4/Lite interconnect with supports transaction overlapping and guarantees the order order of transactions on the bus

Variables:

  • ~.order_m_index_for_s_data – list, FIFOs for each slave which keeps the information about which master accessed slave on this index, to keep the order of transactions coherent

  • ~.order_s_index_for_m_data – list, FIFOs for each master which keeps the information about where master should expect data

HDL params:

  • SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple

  • MASTERS - default value ({0, 1}, {0, 1}) of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • MAX_TRANS_OVERLAP - default value 16 of type int

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
hwtLib.amba.axi_comp.interconnect.matrixR.example_AxiInterconnectMatrixR()[source]

hwtLib.amba.axi_comp.interconnect.matrixW module

class hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixCrossbarB(hwIOCls, hdlName: str | None = None)[source]

Bases: AxiInterconnectMatrixCrossbar

__annotations__ = {}
get_last(hwIO)[source]
class hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixW(hwIOCls, hdlName: str | None = None)[source]

Bases: AxiInterconnectCommon

Write-only AXI3/4/Lite interconnect with supports transaction overlapping and guarantees the order order of transactions on the bus

HDL params:

  • SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple

  • MASTERS - default value ({0, 1}, {0, 1}) of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • MAX_TRANS_OVERLAP - default value 16 of type int

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • AW_AND_W_WORD_TOGETHER - default value True of type bool

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
hwtLib.amba.axi_comp.interconnect.matrixW.example_AxiInterconnectMatrixW()[source]