hwtLib.amba.axi_comp.interconnect package¶
This package is dedicated to inteconnects for AXI interfaces.
Submodules¶
hwtLib.amba.axi_comp.interconnect.base module¶
- class hwtLib.amba.axi_comp.interconnect.base.AxiInterconnectBase(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Abstract class for axi interconnects
hwtLib.amba.axi_comp.interconnect.common module¶
- class hwtLib.amba.axi_comp.interconnect.common.AxiInterconnectCommon(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusInterconnect
hwtLib.amba.axi_comp.interconnect.matrix module¶
- class hwtLib.amba.axi_comp.interconnect.matrix.AxiInterconnectMatrix(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiInterconnectCommon
Matrix style interconnect for AXI-3/4/Lite interfaces
- Variables
~.SLAVES – list of configuration of slave interfaces, configuration is tuple (address, size)
~.MASTERS – list of configuration of master interfaces, configuration is ALL if the master has visibility to all slaves or tuple of flags, where True means the master has visibility to slave on this index
~.AW_AND_W_WORD_TOGETHER – configures if supports AXI AW and W first word in a single clock cycle (if False the W first word must arrive after AW word)
- HDL params
SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple
MASTERS - default value ({(1, ‘RW’), (0, ‘READ’)},) of type tuple
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
MAX_TRANS_OVERLAP - default value 16 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
AW_AND_W_WORD_TOGETHER - default value True of type bool
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_0 - of type hwtLib.amba.axi4.Axi4 - SLAVE
m_0 - of type hwtLib.amba.axi4.Axi4 - MASTER
m_1 - of type hwtLib.amba.axi4.Axi4 - MASTER
- HDL components
r_interconnects_0 - of type hwtLib.amba.axi_comp.interconnect.matrixR.AxiInterconnectMatrixR
w_interconnects_0 - of type hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixW
- configure_sub_interconnect(master_indexes: Set[int], slave_indexes: Set[int], sub_interconnect: Union[AxiInterconnectMatrixR, AxiInterconnectMatrixW]) List[Tuple[AxiInterconnectCommon, INTF_DIRECTION, int, int]] [source]¶
- Note
sub interconnect are used if there are distinct group of masters and slaves in order to avoid unnecessary logic
- Returns
tuples (sub_interconnect, SLAVE/MASTER, index of interface on this component, index of interface on sub_interconnect)
hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar module¶
- class hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar.AxiInterconnectMatrixAddrCrossbar(axi_addr_cls)[source]¶
Bases:
Unit
Component which implements N to M crossbar for AXI address channel. If there are multiple masters connected to any slave the access is mannaged by round-robin.
- Variables
~.order_s_index_for_m_data_out – handshaked interface with index of slave for each master, data is send on start of the transaction
~.order_m_index_for_s_data_out – handshaked interface with index of master for each slave, data is send on start of the transaction
- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4_addr’> of type type
SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple
MASTERS - default value ({0, 1}, {0, 1}) of type tuple
ADDR_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
USER_WIDTH - default value 0 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_0 - of type hwtLib.amba.axi4.Axi4_addr - SLAVE
s_1 - of type hwtLib.amba.axi4.Axi4_addr - SLAVE
m_0 - of type hwtLib.amba.axi4.Axi4_addr - MASTER
m_1 - of type hwtLib.amba.axi4.Axi4_addr - MASTER
order_m_index_for_s_data_out_0 - of type hwt.interfaces.std.Handshaked - MASTER
order_m_index_for_s_data_out_1 - of type hwt.interfaces.std.Handshaked - MASTER
order_s_index_for_m_data_out_0 - of type hwt.interfaces.std.Handshaked - MASTER
order_s_index_for_m_data_out_1 - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
gen_s_0_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_s_1_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
- addr_handler_N_to_M(master_addr_channels, slave_addr_channels, order_m_index_for_s_data_in, order_s_index_for_m_data_in)[source]¶
for each slave use roundrobin to select the master and store indexes of master and slave for later use
- addr_handler_build_addr_mux(slv_addr_tmp, master_addr_channels, addr_assignments, isSelectedFlags)[source]¶
build all master addr to this slave mux
- propagate_addr(master_addr_channels, slave_addr_channels) List[List[Tuple[RtlSignal, HdlAssignmentContainer]]] [source]¶
- Returns
matrix of tuple(addr select, addr assignment) for all masters and slaves (master X slave)
hwtLib.amba.axi_comp.interconnect.matrixCrossbar module¶
- class hwtLib.amba.axi_comp.interconnect.matrixCrossbar.AxiInterconnectMatrixCrossbar(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Crossbar for AXI-Stream like interfaces where internal switch box can be driven by
- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4_r’> of type type
INPUT_CNT - default value 2 of type int
OUTPUTS - default value [{0, 1}, {0, 1}] of type list
ID_WIDTH - default value 6 of type int
DATA_WIDTH - default value 64 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn_0 - of type hwtLib.amba.axi4.Axi4_r - SLAVE
dataIn_1 - of type hwtLib.amba.axi4.Axi4_r - SLAVE
dataOut_0 - of type hwtLib.amba.axi4.Axi4_r - MASTER
dataOut_1 - of type hwtLib.amba.axi4.Axi4_r - MASTER
order_dout_index_for_din_in_0 - of type hwt.interfaces.std.Handshaked - SLAVE
order_dout_index_for_din_in_1 - of type hwt.interfaces.std.Handshaked - SLAVE
order_din_index_for_dout_in_0 - of type hwt.interfaces.std.Handshaked - SLAVE
order_din_index_for_dout_in_1 - of type hwt.interfaces.std.Handshaked - SLAVE
- connection_handler_N_to_M(dataOut_channels, dataIn_channels, order_dout_index_for_din, order_din_index_for_dout)[source]¶
hwtLib.amba.axi_comp.interconnect.matrixR module¶
- class hwtLib.amba.axi_comp.interconnect.matrixR.AxiInterconnectMatrixR(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiInterconnectCommon
Read only AXI3/4/Lite interconnect with supports transaction overlapping and guarantees the order order of transactions on the bus
- Variables
~.order_m_index_for_s_data – list, FIFOs for each slave which keeps the information about which master accessed slave on this index, to keep the order of transactions coherent
~.order_s_index_for_m_data – list, FIFOs for each master which keeps the information about where master should expect data
- HDL params
SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple
MASTERS - default value ({0, 1}, {0, 1}) of type tuple
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
MAX_TRANS_OVERLAP - default value 16 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_0 - of type hwtLib.amba.axi4.Axi4 - SLAVE
s_1 - of type hwtLib.amba.axi4.Axi4 - SLAVE
m_0 - of type hwtLib.amba.axi4.Axi4 - MASTER
m_1 - of type hwtLib.amba.axi4.Axi4 - MASTER
- HDL components
order_m_index_for_s_data_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_m_index_for_s_data_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_data_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_data_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
addr_crossbar - of type hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar.AxiInterconnectMatrixAddrCrossbar
data_crossbar - of type hwtLib.amba.axi_comp.interconnect.matrixCrossbar.AxiInterconnectMatrixCrossbar
hwtLib.amba.axi_comp.interconnect.matrixW module¶
- class hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixCrossbarB(intfCls, hdl_name_override: Optional[str] = None)[source]¶
- class hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixW(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiInterconnectCommon
Write-only AXI3/4/Lite interconnect with supports transaction overlapping and guarantees the order order of transactions on the bus
- HDL params
SLAVES - default value ((4096, 4096), (8192, 4096)) of type tuple
MASTERS - default value ({0, 1}, {0, 1}) of type tuple
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
MAX_TRANS_OVERLAP - default value 16 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
AW_AND_W_WORD_TOGETHER - default value True of type bool
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_0 - of type hwtLib.amba.axi4.Axi4 - SLAVE
s_1 - of type hwtLib.amba.axi4.Axi4 - SLAVE
m_0 - of type hwtLib.amba.axi4.Axi4 - MASTER
m_1 - of type hwtLib.amba.axi4.Axi4 - MASTER
- HDL components
order_m_index_for_s_data_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_m_index_for_s_data_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_m_index_for_s_b_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_m_index_for_s_b_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_data_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_data_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_b_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
order_s_index_for_m_b_1 - of type hwtLib.handshaked.fifo.HandshakedFifo
addr_crossbar - of type hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar.AxiInterconnectMatrixAddrCrossbar
data_crossbar - of type hwtLib.amba.axi_comp.interconnect.matrixCrossbar.AxiInterconnectMatrixCrossbar
b_crossbar - of type hwtLib.amba.axi_comp.interconnect.matrixW.AxiInterconnectMatrixCrossbarB
gen_aw_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_aw_reg_1 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_w_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_w_reg_1 - of type hwtLib.amba.axis_comp.reg.AxiSReg
gen_order_s_index_for_m_data_out_0_splitCopy_0 - of type hwtLib.handshaked.splitCopy.HsSplitCopy
gen_order_s_index_for_m_data_out_1_splitCopy_0 - of type hwtLib.handshaked.splitCopy.HsSplitCopy
gen_order_m_index_for_s_data_out_0_splitCopy_0 - of type hwtLib.handshaked.splitCopy.HsSplitCopy
gen_order_m_index_for_s_data_out_1_splitCopy_0 - of type hwtLib.handshaked.splitCopy.HsSplitCopy