hwtLib.amba.axis_comp.frame_join package

Submodules

hwtLib.amba.axis_comp.frame_join.input_reg module

class hwtLib.amba.axis_comp.frame_join.input_reg.FrameJoinInputReg(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Pipeline of registers for AxiStream with keep mask and flushing

HDL params
  • REG_CNT - default value 2 of type int

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value True of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO
schematic
class hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

HDL params
  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO