hwtLib.amba.axis_comp.frame_join package

Submodules

hwtLib.amba.axis_comp.frame_join.input_reg module

class hwtLib.amba.axis_comp.frame_join.input_reg.FrameJoinInputReg(hdlName: str | None = None)[source]

Bases: HwModule

Pipeline of registers for Axi4Stream with keep mask and flushing

HDL params:
  • REG_CNT - default value 2 of type int

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value True of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:
schematic
__annotations__ = {}
class hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:
  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:
  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • keep - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • relict - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}