hwtLib.amba.axis_comp.frame_join package¶
Submodules¶
hwtLib.amba.axis_comp.frame_join.input_reg module¶
- class hwtLib.amba.axis_comp.frame_join.input_reg.FrameJoinInputReg(hdlName: str | None = None)[source]¶
Bases:
HwModulePipeline of registers for Axi4Stream with keep mask and flushing
- HDL params:
REG_CNT - default value 2 of type int
IS_BIGENDIAN - default value False of type bool
USE_STRB - default value False of type bool
USE_KEEP - default value True of type bool
ID_WIDTH - default value 0 of type int
DEST_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
USER_WIDTH - default value 0 of type int
- HDL IO:
clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE
regs_0 - of type hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf - MASTER
regs_1 - of type hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf - MASTER
keep_masks - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE
ready - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE
- __annotations__ = {}¶
- class hwtLib.amba.axis_comp.frame_join.input_reg.UnalignedJoinRegIntf(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶
Bases:
HwIO- HDL params:
IS_BIGENDIAN - default value False of type bool
USE_STRB - default value False of type bool
USE_KEEP - default value False of type bool
ID_WIDTH - default value 0 of type int
DEST_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
USER_WIDTH - default value 0 of type int
- HDL IO:
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN
keep - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
relict - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
- __annotations__ = {}¶