hwtLib.examples.operators package¶

Submodules¶

hwtLib.examples.operators.concat module¶

class hwtLib.examples.operators.concat.ConcatAssign(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
a1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
a2 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
a3 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
a_in - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

schematic

class hwtLib.examples.operators.concat.ConcatIndexAssignMix0(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
a_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
b_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
b_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
b_2 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
b_3 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.operators.concat.ConcatIndexAssignMix1(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a_2 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a_3 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
b_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER

schematic

class hwtLib.examples.operators.concat.ConcatIndexAssignMix2(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
a_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE
a_2 - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
b_0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
b_1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

schematic

class hwtLib.examples.operators.concat.ConcatIndexAssignMix3(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
port - of type hwt.interfaces.std.BramPort_withoutClk - SLAVE

schematic

class hwtLib.examples.operators.concat.SimpleConcat(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a2 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a3 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
a_out - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

schematic

hwtLib.examples.operators.indexing module¶

class hwtLib.examples.operators.indexing.AssignmentToRegIndex(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER

schematic

class hwtLib.examples.operators.indexing.IndexingInernJoin(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.operators.indexing.IndexingInernRangeSplit(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

schematic

class hwtLib.examples.operators.indexing.IndexingInternSplit(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER

schematic

class hwtLib.examples.operators.indexing.SimpleIndexingJoin(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

class hwtLib.examples.operators.indexing.SimpleIndexingRangeJoin(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE

schematic

class hwtLib.examples.operators.indexing.SimpleIndexingSplit(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic