hwtLib.examples.mem package¶

Examples of various memories.

Submodules¶

hwtLib.examples.mem.avalonmm_ram module¶

class hwtLib.examples.mem.avalonmm_ram.AvalonMmBRam(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL params

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 0 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.avalon.mm.AvalonMM - SLAVE

HDL components

ram - of type hwtLib.mem.ram.RamSingleClock
gen_s_avmm_to_axi4_0 - of type hwtLib.avalon.mmToAxi.AvalonMm_to_Axi4
gen_s_axi_to_AxiLite_0 - of type hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite
decoder - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

hwtLib.examples.mem.axi_ram module¶

class hwtLib.examples.mem.axi_ram.Axi4BRam(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL params

ADDR_WIDTH - default value 10 of type int
DATA_WIDTH - default value 512 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE

HDL components

ram - of type hwtLib.mem.ram.RamSingleClock
gen_s_axi_to_AxiLite_0 - of type hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite
decoder - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

hwtLib.examples.mem.bram_wire module¶

class hwtLib.examples.mem.bram_wire.BramWire(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.BramPort_withoutClk - SLAVE
dout - of type hwt.interfaces.std.BramPort_withoutClk - MASTER

schematic

class hwtLib.examples.mem.bram_wire.BramWireTC(methodName='runTest')[source]¶

Bases: SimTestCase

classmethod setUpClass()[source]¶: Hook method for setting up class fixture before running tests in the class.

test_read()[source]¶

hwtLib.examples.mem.ram module¶

class hwtLib.examples.mem.ram.SimpleAsyncRam(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Note that there is no such a thing in hw yet…

HDL IO

addr_in - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - SLAVE
addr_out - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER

schematic

class hwtLib.examples.mem.ram.SimpleSyncRam(hdl_name_override: Optional[str] = None)[source]¶

Bases: SimpleAsyncRam

HDL IO

addr_in - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - SLAVE
addr_out - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

schematic

hwtLib.examples.mem.reg module¶

note: everything in hwtLib.examples is just example and it is usually more elegant way to do this

class hwtLib.examples.mem.reg.AsyncResetReg(hdl_name_override: Optional[str] = None)[source]¶

Bases: DReg

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.mem.reg.DDR_Reg(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Double Data Rate register

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER

schematic

class hwtLib.examples.mem.reg.DReg(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Basic d flip flop

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.mem.reg.DReg_asyncRst(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.mem.reg.DoubleDReg(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

reg0 - of type hwtLib.examples.mem.reg.DReg
reg1 - of type hwtLib.examples.mem.reg.DReg

schematic

class hwtLib.examples.mem.reg.LatchReg(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
en - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

class hwtLib.examples.mem.reg.OptimizedOutReg(hdl_name_override: Optional[str] = None)[source]¶

Bases: DReg

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.mem.reg.RegWhereNextIsOnlyOutput(hdl_name_override: Optional[str] = None)[source]¶

Bases: DReg

(This is an error example)

hwtLib.examples.mem.rom module¶

class hwtLib.examples.mem.rom.SimpleRom(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER

schematic

class hwtLib.examples.mem.rom.SimpleSyncRom(hdl_name_override: Optional[str] = None)[source]¶

Bases: SimpleRom

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

schematic