hwtLib.examples.mem package

Examples of various memories.

Submodules

hwtLib.examples.mem.avalonmm_ram module

class hwtLib.examples.mem.avalonmm_ram.AvalonMmBRam(hdlName: str | None = None)

Bases: HwModule

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 0 of type int

• waitRequestAllowance - default value 0 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.avalon.mm.AvalonMM - SLAVE

HDL components:

• ram - of type hwtLib.mem.ram.RamSingleClock

• gen_s_avmm_to_axi4_0 - of type hwtLib.avalon.mmToAxi.AvalonMm_to_Axi4

• gen_s_axi_to_AxiLite_0 - of type hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite

• decoder - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

__annotations__ = {}

hwtLib.examples.mem.axi_ram module

class hwtLib.examples.mem.axi_ram.Axi4BRam(hdlName: str | None = None)

Bases: HwModule

HDL params:

• ADDR_WIDTH - default value 10 of type int

• DATA_WIDTH - default value 512 of type int

• ID_WIDTH - default value 6 of type int

• ADDR_USER_WIDTH - default value 0 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.amba.axi4.Axi4 - SLAVE

HDL components:

• ram - of type hwtLib.mem.ram.RamSingleClock

• gen_s_axi_to_AxiLite_0 - of type hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite

• decoder - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

__annotations__ = {}

hwtLib.examples.mem.bram_wire module

class hwtLib.examples.mem.bram_wire.BramWire(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOBramPort_noClk - SLAVE

• dout - of type hwt.hwIOs.std.HwIOBramPort_noClk - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.bram_wire.BramWireTC(methodName='runTest')

Bases: SimTestCase

__annotations__ = {}

_classSetupFailed = False

_class_cleanups = []

classmethod setUpClass()

Hook method for setting up class fixture before running tests in the class.

test_read()

hwtLib.examples.mem.ram module

class hwtLib.examples.mem.ram.SimpleAsyncRam(hdlName: str | None = None)

Bases: HwModule

Note that there is no such a thing in hw yet…

HDL IO:

• addr_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - SLAVE

• addr_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.ram.SimpleSyncRam(hdlName: str | None = None)

Bases: SimpleAsyncRam

HDL IO:

• addr_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - SLAVE

• addr_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

schematic

__annotations__ = {}

hwtLib.examples.mem.reg module

note:

everything in hwtLib.examples is just example and it is usually more elegant way to do this

class hwtLib.examples.mem.reg.AsyncResetReg(hdlName: str | None = None)

Bases: DReg

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.DDR_Reg(hdlName: str | None = None)

Bases: HwModule

Double Data Rate register

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.DReg(hdlName: str | None = None)

Bases: HwModule

Basic d flip flop

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.DReg_asyncRst(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.DoubleDReg(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:

• reg0 - of type hwtLib.examples.mem.reg.DReg

• reg1 - of type hwtLib.examples.mem.reg.DReg

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.LatchReg(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

• en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.OptimizedOutReg(hdlName: str | None = None)

Bases: DReg

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.reg.RegWhereNextIsOnlyOutput(hdlName: str | None = None)

Bases: DReg

(This is an error example)

__annotations__ = {}

hwtLib.examples.mem.rom module

class hwtLib.examples.mem.rom.SimpleRom(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

schematic

__annotations__ = {}

class hwtLib.examples.mem.rom.SimpleSyncRom(hdlName: str | None = None)

Bases: SimpleRom

HDL IO:

• addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

schematic

__annotations__ = {}