hwtLib.examples.statements package¶

Module dedicated for example usages of hwt statements.

Submodules¶

hwtLib.examples.statements.codeBlockStm module¶

class hwtLib.examples.statements.codeBlockStm.BlockStm_complete_override0(hdl_name_override: Optional[str] = None)[source]¶: Bases: Unit

class hwtLib.examples.statements.codeBlockStm.BlockStm_complete_override1(hdl_name_override: Optional[str] = None)[source]¶: Bases: BlockStm_complete_override0

class hwtLib.examples.statements.codeBlockStm.BlockStm_complete_override2(hdl_name_override: Optional[str] = None)[source]¶: Bases: BlockStm_complete_override0

class hwtLib.examples.statements.codeBlockStm.BlockStm_nop_val(hdl_name_override: Optional[str] = None)[source]¶: Bases: BlockStm_nop_val_optimized_out

class hwtLib.examples.statements.codeBlockStm.BlockStm_nop_val_optimized_out(hdl_name_override: Optional[str] = None)[source]¶: Bases: BlockStm_complete_override0

hwtLib.examples.statements.constCondition module¶

class hwtLib.examples.statements.constCondition.ConstCondition(hdl_name_override: Optional[str] = None)[source]¶: Bases: Unit

class hwtLib.examples.statements.constCondition.ConstConditionTC(methodName='runTest')[source]¶

Bases: SimTestCase

classmethod setUpClass()[source]¶: Hook method for setting up class fixture before running tests in the class.

test_reg_update()[source]¶

hwtLib.examples.statements.constCondition.main()[source]¶

hwtLib.examples.statements.constDriver module¶

class hwtLib.examples.statements.constDriver.ConstDriverUnit(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

out0 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
out1 - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

hwtLib.examples.statements.forLoopCntrl module¶

class hwtLib.examples.statements.forLoopCntrl.StaticForLoopCntrl(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL params

ITERATIONS - default value 15 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
cntrl - of type hwt.interfaces.std.HandshakeSync - SLAVE
index - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
body - of type hwt.interfaces.std.HandshakeSync - MASTER
bodyBreak - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

hwtLib.examples.statements.fsm module¶

class hwtLib.examples.statements.fsm.FsmExample(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER

schematic

class hwtLib.examples.statements.fsm.HadrcodedFsmExample(hdl_name_override: Optional[str] = None)[source]¶

Bases: FsmExample

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER

schematic

hwtLib.examples.statements.ifStm module¶

class hwtLib.examples.statements.ifStm.IfStatementPartiallyEnclosed(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatement(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatement2(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatement2b(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatement2c(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatement3(hdl_name_override: Optional[str] = None)[source]¶

Bases: SimpleIfStatement

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatementMergable(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatementMergable1(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
e - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatementMergable2(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
d - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
e - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
f - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatementPartialOverride(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.statements.ifStm.SimpleIfStatementPartialOverrideNopVal(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
e - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

hwtLib.examples.statements.switchStm module¶

class hwtLib.examples.statements.switchStm.SwitchStmUnit(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Example which is using switch statement to create multiplexer

HDL IO

sel - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - SLAVE
out - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

schematic

hwtLib.examples.statements.vldMaskConflictsResolving module¶

class hwtLib.examples.statements.vldMaskConflictsResolving.VldMaskConflictsResolving(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Example how invalid value of condition does not matter if it has no effect on result

HDL IO

a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
c - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic