hwtLib.handshaked package

This package is dedicated to components and utilites realated to interfaces which are using handshake synchronization (ready + valid signals). Most of the components will work for any interface inheriting from hwt.hwIOs.std.HandshakeSync

Submodules

hwtLib.handshaked.builder module

class hwtLib.handshaked.builder.HsBuilder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)

Bases: AbstractStreamBuilder

Helper class which simplifies building of large stream paths

FifoAsyncCls

alias of HsFifoAsync

FifoCls

alias of HandshakedFifo

JoinExplicitCls = NotImplemented

JoinFairCls

alias of HsJoinFairShare

JoinPrioritizedCls

alias of HsJoinPrioritized

RegCls

alias of HandshakedReg

ResizerCls

alias of HsResizer

SplitCopyCls

alias of HsSplitCopy

SplitFairCls

alias of HsSplitFair

SplitPrioritizedCls

alias of HsSplitPrioritized

SplitSelectCls

alias of HsSplitSelect

__annotations__ = {}

to_axis(MAX_FRAME_WORDS=None, IN_TIMEOUT=None)

hwtLib.handshaked.cdc module

class hwtLib.handshaked.cdc.HandshakeFSM(hdlName: str | None = None)

Bases: HwModule

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• ack - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.handshaked.cdc.HandshakedCdc(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

CDC (Clock Domain Crossing) for handshaked interface

HDL params:

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

• DATA_RESET_VAL - default value None of type None

• IN_FREQ - default value 100000000 of type int

• OUT_FREQ - default value 200000000 of type int

HDL IO:

• dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

HDL components:

• in_ack_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen

• out_en_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen

• tx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM

• rx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM

schematic

__annotations__ = {}

create_data_reg(name_prefix, clk=None, rst=None)

Create a registers for data signals with default values from hwt.hwModule.HwModule parameters and with specified clk/rst

propagate_clk(m: CdcPulseGen, reverse=False)

propagate_in_clk(u)

propagate_out_clk(u)

hwtLib.handshaked.cdc.example_HandshakedCdc()

hwtLib.handshaked.compBase module

class hwtLib.handshaked.compBase.HandshakedCompBase(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HwModule

Abstract class for components which has HwIODataRdVld interface as main

__annotations__ = {}

__init__(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Parameters:

hshwIO – class of interface which should be used as interface of this unit

get_data(hwIO: HwIORdVldSync) → List[HwIO]

classmethod get_ready_signal(hwIO: HwIORdVldSync) → HwIOSignal

classmethod get_valid_signal(hwIO: HwIORdVldSync) → HwIOSignal

hwtLib.handshaked.dataRdVldToAxi4Stream module

class hwtLib.handshaked.dataRdVldToAxi4Stream.DataRdVldToAxi4Stream(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Pack raw input data from hwt.hwIOs.std.HwIODataRdVld interface into Axi4Stream frames according to an input timeout or max frame size specification

HDL params:

• IN_TIMEOUT - default value 10 of type intnumber of clk ticks until the actual frame is closed with the last word when if there are not input data

• MAX_FRAME_WORDS - default value None of type Nonemaximum number of words in frame

• DATA_WIDTH - default value 64 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

HDL components:

• r - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__annotations__ = {}

construct_timeout_cntr_and_in_reg()

hwtLib.handshaked.dataRdVldToAxi4Stream._example_HandshakedToAxi4Stream()

hwtLib.handshaked.fifo module

class hwtLib.handshaked.fifo.HandshakedFifo(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Synchronous FIFO for handshaked interfaces :note: 1clk to write, 1clk to load to output reg (and then 1clk to read next data).

HDL params:

• DEPTH - default value 2 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 4 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

HDL components:

• r0 - of type hwtLib.handshaked.reg.HandshakedReg

• r1 - of type hwtLib.handshaked.reg.HandshakedReg

schematic

FIFO_CLS

alias of Fifo

NON_DATA_BITS_CNT = 2

REG_CLS

alias of HandshakedReg

__annotations__ = {}

_connect_fifo_in()

_connect_fifo_out(out_clk: HwIOClk, out_rst: HwIORst | HwIORst_n | None)

_connect_size_and_space(out_vld: HBitsRtlSignal | None, fifo: Fifo | None)

_connect_size_and_space_no_fifo()

variant of _connect_size_and_space() for the case that there is no fifo an registers are used instead

_declr_io()

hwImpl(clk_rst: Tuple[Tuple[HwIOClk, HwIORst | HwIORst_n], Tuple[HwIOClk, HwIORst | HwIORst_n]] | None = None)

Parameters:

clk_rst – optional tuple ((inClk, inRst), (outClk, outRst))

hwtLib.handshaked.fifo._example_HandshakedFifo()

hwtLib.handshaked.fifoAsync module

class hwtLib.handshaked.fifoAsync.HsFifoAsync(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedFifo

Asynchronous FIFO using BRAM/LUT memory, based on:

HDL params:

• DEPTH - default value 5 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

• IN_FREQ - default value 100000000 of type int

• OUT_FREQ - default value 100000000 of type int

HDL IO:

• dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

HDL components:

• fifo - of type hwtLib.mem.fifoAsync.FifoAsync

schematic

__annotations__ = {}

hwtLib.handshaked.fifoAsync._example_HsFifoAsync()

hwtLib.handshaked.fifoDrop module

class hwtLib.handshaked.fifoDrop.HandshakedFifoDrop(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedFifo

FIFO for handsahaked interface which allows to discard/commit written data

HDL params:

• DEPTH - default value 8 of type int

• EXPORT_SIZE - default value True of type bool

• EXPORT_SPACE - default value True of type bool

• INIT_DATA - default value () of type tuple

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 4 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

• size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits, unsigned> - MASTER

• space - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits, unsigned> - MASTER

• dataIn_discard - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dataIn_commit - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

HDL components:

• fifo - of type hwtLib.mem.fifoDrop.FifoDrop

schematic

FIFO_CLS

alias of FifoDrop

__annotations__ = {}

hwtLib.handshaked.fifoDrop._example_HandshakedFifoDrop()

hwtLib.handshaked.hwIOBiDirectional module

class hwtLib.handshaked.hwIOBiDirectional.HwIORdVldSyncBiDirectionalData(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIODataRdVld

hwt.hwIOs.std.HwIODataRdVld interface with data

channels in bout direction

HDL params:

• DATA_WIDTH - default value 64 of type int

HDL IO:

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN (Master=IN)

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

• vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}

_initSimAgent(sim: HdlSimulator)

class hwtLib.handshaked.hwIOBiDirectional.HwIORdVldSyncBiDirectionalDataAgent(sim, hwIO)

Bases: HwIODataRdVldAgent

Simulation agent for HwIORdVldSyncBiDirectionalData interface

Attention:

for monitor number of items in dinData has to match with number of received items

__annotations__ = {}

__init__(sim, hwIO)

Parameters:

rst – tuple (rst signal, rst_negated flag)

getMonitors()

Note:

use only before running simulator

get_data()

extract data from interface

notReset()

Untility function returning state of the associated reset signal

onDriverWriteAck()

read din

onMonitorReady()

write din

set_data(data)

write data to interface

hwtLib.handshaked.joinFair module

class hwtLib.handshaked.joinFair.HsJoinFairShare(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HsJoinPrioritized

Join multiple input streams into single output stream. Priority is changing every clock period. If prioritized input is not sending valid data, input with lowest index and valid is used.

Note:

combinational

__annotations__ = {}

inputMuxLogic(isSelectedFlags)

isSelectedLogic(din_vlds, dout_rd, selectedOneHot)

Resolve isSelected signal flags for each input, when isSelected flag signal is 1 it means input has clearance to make transaction

static priorityAck(priorityReg, vldSignals, index)

Generate ack logic for selected input

Parameters:

• priorityReg – priority register with one hot encoding, 1 means input of this index should have be prioritized.

• vldSignals – list of vld signals of input

• index – index of input for which you wont get ack logic

Returns:

ack signal for this input

hwtLib.handshaked.joinFair._example_HsJoinFairShare()

hwtLib.handshaked.joinPrioritized module

class hwtLib.handshaked.joinPrioritized.HsJoinPrioritized(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Join input stream to single output stream inputs with lower number has higher priority

HDL params:

• INPUTS - default value 2 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

HDL IO:

• dataIn - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}

dataConnectionExpr(dIn, dOut)

Create connection between input and output interface

hwtLib.handshaked.joinPrioritized._example_HsJoinPrioritized()

hwtLib.handshaked.ramAsAddrDataRdVld module

class hwtLib.handshaked.ramAsAddrDataRdVld.HwIORamRdVldR(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

HwIODataRdVld RAM port

HDL params:

• ADDR_WIDTH - default value 8 of type int

• DATA_WIDTH - default value 8 of type int

HDL IO:

• addr - of type hwt.hwIOs.std.HwIODataRdVld - UNKNOWN

• data - of type hwt.hwIOs.std.HwIODataRdVld - UNKNOWN (Master=IN)

__annotations__ = {}

_initSimAgent(sim: HdlSimulator)

class hwtLib.handshaked.ramAsAddrDataRdVld.RamAsAddrDataRdVld(hdlName: str | None = None)

Bases: HwModule

Converter from a single ram port to handshaked interfaces

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

• HAS_R - default value True of type bool

• HAS_W - default value True of type bool

• HAS_BE - default value False of type bool

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• r - of type hwtLib.handshaked.ramAsAddrDataRdVld.HwIORamRdVldR - SLAVE

• w - of type hwtLib.commonHwIO.addr_data.HwIOAddrDataRdVld - SLAVE

• ram - of type hwt.hwIOs.std.HwIOBramPort_noClk - MASTER

schematic

__annotations__ = {}

read_logic(r: HwIORamRdVldR, ram: HwIOBramPort_noClk)

hwtLib.handshaked.reg module

class hwtLib.handshaked.reg.HandshakedReg(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Register for HwIODataRdVld interfaces

HDL params:

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

• LATENCY - default value 1 of type int

• DELAY - default value 0 of type int

• INIT_DATA - default value () of type tuplea reset value of register (data is transferred from this register after reset) (an item for each stage of register, typically just 1 item) e.g. if register has latency=1 and interface has just data:uint8_t signal the INIT_DATA will be in format ((0,),)

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}

_implLatencyAndDelay(inVld: RtlSignal, inRd: RtlSignal, inData: List[RtlSignal], outVld: RtlSignal, outRd: RtlSignal, prefix: str, initData: list, hasInit: bool)

Create a register pipe

See:

For param description see HandshakedReg._impl_latency()

_implReadyChainBreak(in_vld: RtlSignal, in_rd: RtlSignal, in_data: List[RtlSignal], out_vld: RtlSignal, out_rd: RtlSignal, prefix: str, initData: list, hasInit: bool)

Two sets of registers 0. is prioritized 1. is used as a backup The in_rd is not combinationally connected to out_rd The out_vld is not combinationally connected to in_vld

See:

For param description see HandshakedReg._impl_latency()

_implSkidBuff(inVld: RtlSignal, inRd: RtlSignal, inData: List[RtlSignal], outVld: RtlSignal, outRd: RtlSignal)

latency 0-1, dealy 0, pass input directly to output and if output.ready=0, store data in internal buffer and wait until it is consumed before setting input.ready=1 again. Breaks ready chain but has combination path on “valid”.

https://github.com/j-marjanovic/chisel-stuff/blob/master/example-14-pcie-endpoint/src/main/scala/pcie_endpoint/SkidBuffer.scala

_impl_latency(inVld: RtlSignal, inRd: RtlSignal, inData: List[RtlSignal], outVld: RtlSignal, outRd: RtlSignal, prefix: str, initData: list, hasInit: bool)

Create a normal handshaked register

Parameters:

• inVld – input valid signal (1 if producer is sending data)

• inRd – input ready signal (send 1 if we are ready to receive the data)

• inData – list of input data signals

• outVld – output valid signal (1 if we are sending valid data)

• outRd – output ready signal (1 if consummer is ready to receive the data)

• prefix – name prefix used for internal signals

• initData – list of init data for each data signal on iterface

hwtLib.handshaked.reg._example_HandshakedReg()

hwtLib.handshaked.resizer module

class hwtLib.handshaked.resizer.HsResizer(hshwIO: HwIORdVldSync, scale, inHwIOConfigFn, outHwIOConfigFn)

Bases: HandshakedCompBase

Resize width of handshaked interface

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}

__init__(hshwIO: HwIORdVldSync, scale, inHwIOConfigFn, outHwIOConfigFn)

Parameters:

• hshwIO – class of interface which should be used as interface of this unit

• scale – tuple (in scale, out scale) one of scales has to be 1, f. e. (1,2) means output will be 2x wider

• inHwIOConfigFn – function inHwIOConfigFn(input interface) which will be applied on dataIn

• outHwIOConfigFn – function outHwIOConfigFn(input interface) which will be applied on dataOut

_downscale(factor: int)

_upscale(factor: int)

_upscaleDataPassLogic(inputRegs_cntr: RtlSignal, ITEMS: int)

hwtLib.handshaked.resizer._example_HsResizer()

hwtLib.handshaked.splitCopy module

class hwtLib.handshaked.splitCopy.HsSplitCopy(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Clone input stream to n identical output streams transaction is made in all interfaces or none of them

HDL params:

• OUTPUTS - default value 2 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

HDL IO:

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

schematic

__annotations__ = {}

hwtLib.handshaked.splitCopy._example_HsSplitCopy()

hwtLib.handshaked.splitFair module

class hwtLib.handshaked.splitFair.HsSplitFair(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HsSplitCopy

Split input stream to outputs, select single output for every input data based on priority.

Priority is changing every clock If prioritized output is not ready, input with lowest index and ready is used

Variables:

~.selectedOneHot – handshaked interface with one hot encoded index of selected output

HDL params:

• OUTPUTS - default value 2 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

• EXPORT_SELECTED - default value True of type bool

HDL IO:

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• selectedOneHot - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}

isSelectedLogic(din)

Resolve isSelected signal flags for each input, when isSelected flag signal is 1 it means input has clearance to make transaction

hwtLib.handshaked.splitFair._example_HsSplitFair()

hwtLib.handshaked.splitPrioritized module

class hwtLib.handshaked.splitPrioritized.HsSplitPrioritized(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HsSplitCopy

Split input stream to N output streams. Data is send to output interface which is ready and has lowest index.

HDL params:

• OUTPUTS - default value 4 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

HDL IO:

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

schematic

__annotations__ = {}

hwtLib.handshaked.splitPrioritized._example_HsSplitPrioritized()

hwtLib.handshaked.splitSelect module

class hwtLib.handshaked.splitSelect.HsSplitSelect(hshwIO: Type[HwIORdVldSync], hdlName: str | None = None)

Bases: HandshakedCompBase

Split data from input interface to N output interfaces based on explicit output index provided by select interface.

HDL params:

• OUTPUTS - default value 3 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• DATA_WIDTH - default value 64 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• selectOneHot - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:

• selReg - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__annotations__ = {}

_select_consume_en()

hwtLib.handshaked.splitSelect._example_HsSplitSelect()

hwtLib.handshaked.storedBurst module

class hwtLib.handshaked.storedBurst.HandshakedStoredBurst(hwIOCls=<class 'hwt.hwIOs.std.HwIODataRdVld'>, hdlName: str | None = None)

Bases: HwModule

This units send data stored in property DATA over axi-stream interface

HDL params:

• DATA_WIDTH - default value 64 of type int

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataRdVld’> of type type

• REPEAT - default value False of type bool

• DATA - default value (72, 101, 108, 108, 111, 32, 119, 111, 114, 108, 100) of type tuple

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}

__init__(hwIOCls=<class 'hwt.hwIOs.std.HwIODataRdVld'>, hdlName: str | None = None)

dataRd()

nextWordIndexLogic(wordIndex: RtlSignal)

set_data(hwIO: HwIODataRdVld, d)

hwtLib.handshaked.streamNode module

class hwtLib.handshaked.streamNode.ExclusiveStreamGroups(iterable=(), /)

Bases: list

list of tuples (cond, StreamNode instance) Only one stream from this group can be activated at the time

__hash__()

Return hash(self).

ack() → RtlSignal

Returns:

expression which’s value is high when transaction can be made over at least on child streaming node

sync(enSig=None) → List[HdlAssignmentContainer]

Create synchronization logic between streams (generate valid/ready synchronization logic for interfaces)

Parameters:

enSig – optional signal to enable this group of nodes

Returns:

list of assignments which are responsible for synchronization of streams

class hwtLib.handshaked.streamNode.StreamNode(masters: List[HwIO | Tuple[RtlSignal | int, RtlSignal | int]] | None = None, slaves: List[HwIO | Tuple[RtlSignal | int, RtlSignal | int]] | None = None, extraConds: Dict[HwIO | Tuple[RtlSignal | int, RtlSignal | int], RtlSignal] | None = None, skipWhen: Dict[HwIO | Tuple[RtlSignal | int, RtlSignal | int], RtlSignal] | None = None)

Bases: object

Group of stream master and slave interfaces to synchronize them to each other

Variables:

• ~.masters – list of unique interfaces which are inputs into this node

• ~.slaves – list of unique interfaces which are outputs of this node

• ~.extraConds – dict {interface : extraConditionSignal} where extra conditions will be added to expression for channel enable. For master it means it will obtain ready=1 only if extraConditionSignal is 1. For slave it means it will obtain valid=1 only if extraConditionSignal is 1. All interfaces have to wait on each other so if an extraCond!=1 it causes blocking on all interfaces if not overridden by skipWhen.

• ~.skipWhen – dict {interface : skipSignal} where if skipSignal is high, the interface is disconnected from stream sync node and others does not have to wait for it (master does not need to have valid and slave ready)

Note:

instead of interface it is possible to use tuple (valid, ready) signal, this tuple can also be (1, 1) but can only in masters or only in slaves

Attention:

skipWhen has higher priority than extraCond

__init__(masters: List[HwIO | Tuple[RtlSignal | int, RtlSignal | int]] | None = None, slaves: List[HwIO | Tuple[RtlSignal | int, RtlSignal | int]] | None = None, extraConds: Dict[HwIO | Tuple[RtlSignal | int, RtlSignal | int], RtlSignal] | None = None, skipWhen: Dict[HwIO | Tuple[RtlSignal | int, RtlSignal | int], RtlSignal] | None = None)

__repr__()

Return repr(self).

__repr__format_HwIO_list(hwIO_list)

ack() → RtlSignal

Returns:

expression which’s value is high when transaction can be made over interfaces

ackForMaster(master: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal

Returns:

driver of ready signal for master

ackForSlave(slave: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal

Returns:

driver of valid signal for slave

getExtraAndSkip(hwIO: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → Tuple[RtlSignal | None, RtlSignal | None]

Returns:

optional extraCond and skip flags for interface

rd(hwIO: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal

Returns:

ready signal of slave interface for synchronization of othres

sync(enSig: RtlSignal | None = None) → List[HdlAssignmentContainer]

Create synchronization logic between streams (generate valid/ready synchronization logic for interfaces)

Parameters:

enSig – optional signal to enable this node

Returns:

list of assignments which are responsible for synchronization of streams

vld(hwIO: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal

Returns:

valid signal of master interface for synchronization of othres

hwtLib.handshaked.streamNode._exStreamMemberAck(m) → RtlSignal

hwtLib.handshaked.streamNode._get_ready_signal(hwIO: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal

hwtLib.handshaked.streamNode._get_valid_signal(hwIO: HwIO | Tuple[RtlSignal | int, RtlSignal | int]) → RtlSignal