hwtLib.handshaked package¶
This package is dedicated to components and utilites realated to interfaces which are using handshake synchronization (ready + valid signals).
Most of the components will work for any interface inheriting from hwt.interfaces.std.HandshakeSync
Submodules¶
hwtLib.handshaked.builder module¶
- class hwtLib.handshaked.builder.HsBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]¶
Bases:
AbstractStreamBuilder
Helper class which simplifies building of large stream paths
- FifoAsyncCls¶
alias of
HsFifoAsync
- FifoCls¶
alias of
HandshakedFifo
- JoinExplicitCls = NotImplemented¶
- JoinFairCls¶
alias of
HsJoinFairShare
- JoinPrioritizedCls¶
alias of
HsJoinPrioritized
- RegCls¶
alias of
HandshakedReg
- SplitCopyCls¶
alias of
HsSplitCopy
- SplitFairCls¶
alias of
HsSplitFair
- SplitPrioritizedCls¶
alias of
HsSplitPrioritized
- SplitSelectCls¶
alias of
HsSplitSelect
hwtLib.handshaked.cdc module¶
- class hwtLib.handshaked.cdc.HandshakeFSM(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst - of type hwt.interfaces.std.Rst with dtype=<Bits, 1bit> - SLAVE
ack - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.handshaked.cdc.HandshakedCdc(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
CDC (Clock Domain Crossing) for handshaked interface
- HDL params
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
DATA_RESET_VAL - default value None of type None
IN_FREQ - default value 100000000 of type int
OUT_FREQ - default value 200000000 of type int
- HDL IO
dataIn_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
dataIn_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataOut_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
dataOut_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
in_ack_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen
out_en_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen
tx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM
rx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM
- create_data_reg(name_prefix, clk=None, rst=None)[source]¶
Create a registers for data signals with default values from
hwt.synthesizer.unit.Unit
parameters and with specified clk/rst
hwtLib.handshaked.compBase module¶
- class hwtLib.handshaked.compBase.HandshakedCompBase(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Abstract class for components which has Handshaked interface as main
- __init__(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
- Parameters
hsIntfCls – class of interface which should be used as interface of this unit
- get_data(intf: HandshakeSync) List[Interface] [source]¶
- classmethod get_ready_signal(intf: HandshakeSync) Signal [source]¶
- classmethod get_valid_signal(intf: HandshakeSync) Signal [source]¶
hwtLib.handshaked.fifo module¶
- class hwtLib.handshaked.fifo.HandshakedFifo(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Synchronous FIFO for handshaked interfaces
- HDL params
DEPTH - default value 8 of type int
EXPORT_SIZE - default value False of type bool
EXPORT_SPACE - default value False of type bool
INIT_DATA - default value () of type tuple
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
fifo - of type hwtLib.mem.fifo.Fifo
- NON_DATA_BITS_CNT = 2¶
hwtLib.handshaked.fifoAsync module¶
- class hwtLib.handshaked.fifoAsync.HsFifoAsync(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedFifo
Asynchronous FIFO using BRAM/LUT memory, based on:
- HDL params
DEPTH - default value 5 of type int
EXPORT_SIZE - default value False of type bool
EXPORT_SPACE - default value False of type bool
INIT_DATA - default value () of type tuple
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
IN_FREQ - default value 100000000 of type int
OUT_FREQ - default value 100000000 of type int
- HDL IO
dataIn_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
dataOut_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
dataIn_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
fifo - of type hwtLib.mem.fifoAsync.FifoAsync
- _hdl_module_name: Optional[str]¶
- _lazy_loaded: List[Union[Unit, InterfaceBase]]¶
- _name: Optional[str]¶
- _parent: Optional[Unit]¶
hwtLib.handshaked.fifoDrop module¶
- class hwtLib.handshaked.fifoDrop.HandshakedFifoDrop(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedFifo
Fifo for handsahaked interface which allows to discard/commit written data
- HDL params
DEPTH - default value 8 of type int
EXPORT_SIZE - default value True of type bool
EXPORT_SPACE - default value True of type bool
INIT_DATA - default value () of type tuple
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
size - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits, unsigned> - MASTER
space - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits, unsigned> - MASTER
dataIn_discard - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
dataIn_commit - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE
- HDL components
fifo - of type hwtLib.mem.fifoDrop.FifoDrop
- _hdl_module_name: Optional[str]¶
- _lazy_loaded: List[Union[Unit, InterfaceBase]]¶
- _name: Optional[str]¶
- _parent: Optional[Unit]¶
hwtLib.handshaked.handshakedToAxiStream module¶
- class hwtLib.handshaked.handshakedToAxiStream.HandshakedToAxiStream(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Pack raw input data from
hwt.interfaces.std.Handshaked
interface into AxiStream frames according to an input timeout or max frame size specification- HDL params
IN_TIMEOUT - default value 10 of type intnumber of clk ticks until the actual frame is closed with the last word when if there are not input data
MAX_FRAME_WORDS - default value None of type Nonemaximum number of words in frame
DATA_WIDTH - default value 64 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwtLib.amba.axis.AxiStream - MASTER
- HDL components
r - of type hwtLib.handshaked.reg.HandshakedReg
hwtLib.handshaked.intfBiDirectional module¶
- class hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectional(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Handshaked
hwt.interfaces.std.Handshaked
interface with datachannels in bout direction
- HDL params
DATA_WIDTH - default value 64 of type int
- HDL IO
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE (Master=IN)
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
- class hwtLib.handshaked.intfBiDirectional.HandshakedBiDirectionalAgent(sim, intf)[source]¶
Bases:
HandshakedAgent
Simulation agent for
HandshakedBiDirectional
interface- Attention
for monitor number of items in dinData has to match with number of received items
hwtLib.handshaked.joinFair module¶
Bases:
HsJoinPrioritized
Join multiple input streams into single output stream. Priority is changing every clock period. If prioritized input is not sending valid data, input with lowest index and valid is used.
- Note
combinational
Resolve isSelected signal flags for each input, when isSelected flag signal is 1 it means input has clearance to make transaction
Generate ack logic for selected input
- Parameters
priorityReg – priority register with one hot encoding, 1 means input of this index should have be prioritized.
vldSignals – list of vld signals of input
index – index of input for which you wont get ack logic
- Returns
ack signal for this input
hwtLib.handshaked.joinPrioritized module¶
- class hwtLib.handshaked.joinPrioritized.HsJoinPrioritized(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Join input stream to single output stream inputs with lower number has higher priority
- HDL params
INPUTS - default value 2 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
- HDL IO
dataIn_0 - of type hwt.interfaces.std.Handshaked - SLAVE
dataIn_1 - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
hwtLib.handshaked.ramAsHs module¶
- class hwtLib.handshaked.ramAsHs.RamAsHs(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Converter from a single ram port to handshaked interfaces
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
HAS_R - default value True of type bool
HAS_W - default value True of type bool
HAS_BE - default value False of type bool
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
r - of type hwtLib.handshaked.ramAsHs.RamHsR - SLAVE
w - of type hwtLib.common_nonstd_interfaces.addr_data_hs.AddrDataHs - SLAVE
ram - of type hwt.interfaces.std.BramPort_withoutClk - MASTER
- read_logic(r: RamHsR, ram: BramPort_withoutClk)[source]¶
- class hwtLib.handshaked.ramAsHs.RamHsR(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
Handshaked RAM port
- HDL params
ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
- HDL IO
addr - of type hwt.interfaces.std.Handshaked - MASTER
data - of type hwt.interfaces.std.Handshaked - SLAVE (Master=IN)
hwtLib.handshaked.reg module¶
- class hwtLib.handshaked.reg.HandshakedReg(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Register for Handshaked interfaces
- HDL params
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
LATENCY - default value 1 of type int
DELAY - default value 0 of type int
INIT_DATA - default value () of type tuplea reset value of register (data is transfered from this register after reset) (an item for each stage of register, typically just 1 item) e.g. if register has latency=1 and interface has just data:uint8_t signal the INIT_DATA will be in format ((0,),)
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
- _implLatencyAndDelay(inVld: RtlSignal, inRd: RtlSignal, inData: List[RtlSignal], outVld: RtlSignal, outRd: RtlSignal, prefix: str, initData: list, hasInit: bool)[source]¶
Create a register pipe
- See
For param description see
HandshakedReg._impl_latency()
- _implReadyChainBreak(in_vld: RtlSignal, in_rd: RtlSignal, in_data: List[RtlSignal], out_vld: RtlSignal, out_rd: RtlSignal, prefix: str, initData: list, hasInit: bool)[source]¶
Two sets of registers 0. is prioritized 1. is used as a backup The in_rd is not combinationally connected to out_rd The out_vld is not combinationally connected to in_vld
- See
For param description see
HandshakedReg._impl_latency()
- _impl_latency(inVld: RtlSignal, inRd: RtlSignal, inData: List[RtlSignal], outVld: RtlSignal, outRd: RtlSignal, prefix: str, initData: list, hasInit: bool)[source]¶
Create a normal handshaked register
- Parameters
inVld – input valid signal (1 if producer is sending data)
inRd – input ready signal (send 1 if we are ready to receive the data)
inData – list of input data signals
outVld – output valid signal (1 if we are sending valid data)
outRd – output ready signal (1 if consummer is ready to receive the data)
prefix – name prefix used for internal signals
initData – list of init data for each data signal on iterface
hwtLib.handshaked.resizer module¶
- class hwtLib.handshaked.resizer.HsResizer(hsIntfCls, scale, inIntfConfigFn, outIntfConfigFn)[source]¶
Bases:
HandshakedCompBase
Resize width of handshaked interface
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
- __init__(hsIntfCls, scale, inIntfConfigFn, outIntfConfigFn)[source]¶
- Parameters
hsIntfCls – class of interface which should be used as interface of this unit
scale – tuple (in scale, out scale) one of scales has to be 1, f. e. (1,2) means output will be 2x wider
inIntfConfigFn – function inIntfConfigFn(input interface) which will be applied on dataIn
outIntfConfigFn – function outIntfConfigFn(input interface) which will be applied on dataOut
hwtLib.handshaked.splitCopy module¶
- class hwtLib.handshaked.splitCopy.HsSplitCopy(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Clone input stream to n identical output streams transaction is made in all interfaces or none of them
- HDL params
OUTPUTS - default value 2 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
- HDL IO
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut_0 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_1 - of type hwt.interfaces.std.Handshaked - MASTER
hwtLib.handshaked.splitFair module¶
- class hwtLib.handshaked.splitFair.HsSplitFair(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HsSplitCopy
Split input stream to outputs, select single output for every input data based on priority.
Priority is changing every clock If prioritized output is not ready, input with lowest index and ready is used
- Variables
~.selectedOneHot – handshaked interface with one hot encoded index of selected output
- HDL params
OUTPUTS - default value 2 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
EXPORT_SELECTED - default value True of type bool
- HDL IO
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut_0 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_1 - of type hwt.interfaces.std.Handshaked - MASTER
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
selectedOneHot - of type hwt.interfaces.std.Handshaked - MASTER
hwtLib.handshaked.splitPrioritized module¶
- class hwtLib.handshaked.splitPrioritized.HsSplitPrioritized(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HsSplitCopy
Split input stream to N output streams. Data is send to output interface which is ready and has lowest index.
- HDL params
OUTPUTS - default value 4 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
- HDL IO
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut_0 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_1 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_2 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_3 - of type hwt.interfaces.std.Handshaked - MASTER
hwtLib.handshaked.splitSelect module¶
- class hwtLib.handshaked.splitSelect.HsSplitSelect(hsIntfCls: Type[Union[Handshaked, HandshakeSync]], hdl_name_override: Optional[str] = None)[source]¶
Bases:
HandshakedCompBase
Split data from input interface to N output interfaces based on explicit output index provided by select interface.
- HDL params
OUTPUTS - default value 3 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
DATA_WIDTH - default value 64 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
selectOneHot - of type hwt.interfaces.std.Handshaked - SLAVE
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
dataOut_0 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_1 - of type hwt.interfaces.std.Handshaked - MASTER
dataOut_2 - of type hwt.interfaces.std.Handshaked - MASTER
- HDL components
selReg - of type hwtLib.handshaked.reg.HandshakedReg
hwtLib.handshaked.storedBurst module¶
- class hwtLib.handshaked.storedBurst.HandshakedStoredBurst(intfCls=<class 'hwt.interfaces.std.Handshaked'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶
Bases:
Unit
This units send data stored in property DATA over axi-stream interface
- HDL params
DATA_WIDTH - default value 64 of type int
INTF_CLS - default value <class ‘hwt.interfaces.std.Handshaked’> of type type
REPEAT - default value False of type bool
DATA - default value (72, 101, 108, 108, 111, 32, 119, 111, 114, 108, 100) of type tuple
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
dataOut - of type hwt.interfaces.std.Handshaked - MASTER
hwtLib.handshaked.streamNode module¶
- class hwtLib.handshaked.streamNode.ExclusiveStreamGroups(iterable=(), /)[source]¶
Bases:
list
list of tuples (cond, StreamNode instance) Only one stream from this group can be activated at the time
- ack() RtlSignal [source]¶
- Returns
expression which’s value is high when transaction can be made over at least on child streaming node
- sync(enSig=None) List[HdlAssignmentContainer] [source]¶
Create synchronization logic between streams (generate valid/ready synchronization logic for interfaces)
- Parameters
enSig – optional signal to enable this group of nodes
- Returns
list of assignments which are responsible for synchronization of streams
- class hwtLib.handshaked.streamNode.StreamNode(masters: Optional[List[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]]] = None, slaves: Optional[List[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]]] = None, extraConds: Optional[Dict[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]], RtlSignal]] = None, skipWhen: Optional[Dict[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]], RtlSignal]] = None)[source]¶
Bases:
object
Group of stream master and slave interfaces to synchronize them to each other
- Variables
~.masters – interfaces which are inputs into this node
~.slaves – interfaces which are outputs of this node
~.extraConds – {dict interface : extraConditionSignal} where extra conditions will be added to expression for channel enable. For master it means it will obtain ready=1 only if extraConditionSignal is 1. For slave it means it will obtain valid=1 only if extraConditionSignal is 1. All interfaces have to wait on each other so if an extraCond!=1 it causes blocking on all interfaces if not overridden by skipWhen.
~.skipWhen – dict interface : skipSignal where if skipSignal is high interface is disconnected from stream sync node and others does not have to wait on it (master does not need to have valid and slave ready)
- Note
instead of interface it is possilble to use tuple (valid, ready) signal
- Attention
skipWhen has higher priority
- __init__(masters: Optional[List[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]]] = None, slaves: Optional[List[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]]] = None, extraConds: Optional[Dict[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]], RtlSignal]] = None, skipWhen: Optional[Dict[Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]], RtlSignal]] = None)[source]¶
- __repr__format_intf_list(intf_list)¶
- ack() RtlSignal [source]¶
- Returns
expression which’s value is high when transaction can be made over interfaces
- ackForMaster(master: Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]) RtlSignal [source]¶
- Returns
driver of ready signal for master
- ackForSlave(slave: Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]) RtlSignal [source]¶
- Returns
driver of valid signal for slave
- getExtraAndSkip(intf: Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]) Tuple[Optional[RtlSignal], Optional[RtlSignal]] [source]¶
- Returns
optional extraCond and skip flags for interface
- rd(intf: Union[Interface, Tuple[Union[RtlSignal, int], Union[RtlSignal, int]]]) RtlSignal [source]¶
- Returns
ready signal of slave interface for synchronization of othres
- sync(enSig: Optional[RtlSignal] = None) List[HdlAssignmentContainer] [source]¶
Create synchronization logic between streams (generate valid/ready synchronization logic for interfaces)
- Parameters
enSig – optional signal to enable this node
- Returns
list of assignements which are responsible for synchronization of streams