hwtLib.mem.extern package

Submodules

hwtLib.mem.extern.migUserPort module

class hwtLib.mem.extern.migUserPort.MIG_CMD

Bases: object

READ = 1

WRITE = 0

WR_BYTES = 3

class hwtLib.mem.extern.migUserPort.MigUserPort(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)

Bases: Interface

Interface used to control Xilinx MIG (Memory Interface Generator) DDR4 controller

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf p. 122

class hwtLib.mem.extern.migUserPort.MigUserPortRD(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)

Bases: Interface

class hwtLib.mem.extern.migUserPort.MigUserPortWDF(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)

Bases: Interface