hwtLib.mem.atomic package

Submodules

hwtLib.mem.atomic.flipCntr module

class hwtLib.mem.atomic.flipCntr.FlipCntr(hdlName: str | None = None)

Bases: HwModule

Counter with FlipRegister which is form memory with atomic access

interface doFilip drives switching of memories in flip register dataIn has higher priority than doIncr

HDL params:

• DATA_WIDTH - default value 18 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• doIncr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• doFlip - of type hwt.hwIOs.std.HwIORdVldSync - SLAVE

• data - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE

HDL components:

• cntr - of type hwtLib.mem.atomic.flipReg.FlipRegister

schematic

__annotations__ = {}

dataHanldler()

flipHandler()

hwtLib.mem.atomic.flipRam module

class hwtLib.mem.atomic.flipRam.FlipRam(hdlName: str | None = None)

Bases: HwModule

Switchable RAM, there are two memories and two sets of ports, Each set of ports is every time connected to opposite ram. By select you can choose between RAMs.

This component is meant to be form of synchronization. Example first RAM is connected to first set of ports, writer performs actualizations on first RAM and reader reads data from second ram by second set of ports.

Then select is set and access is flipped. Reader now has access to RAM 0 and writer to RAM 1.

HDL params:

• ADDR_WIDTH - default value 10 of type int

• DATA_WIDTH - default value 64 of type int

• PORT_CNT - default value 1 of type int

• HAS_BE - default value False of type bool

• MAX_BLOCK_DATA_WIDTH - default value None of type None

• INIT_DATA - default value None of type None

• READ_LATENCY - default value 1 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• firstA - of type hwt.hwIOs.std.HwIOBramPort_noClk - SLAVE

• secondA - of type hwt.hwIOs.std.HwIOBramPort_noClk - SLAVE

• select_sig - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

HDL components:

• ram0 - of type hwtLib.mem.ram.RamSingleClock

• ram1 - of type hwtLib.mem.ram.RamSingleClock

schematic

__annotations__ = {}

hwtLib.mem.atomic.flipReg module

class hwtLib.mem.atomic.flipReg.FlipRegister(hdlName: str | None = None)

Bases: HwModule

Switchable register, there are two registers and two sets of ports, Each set of ports is every time connected to opposite reg. By select you can choose between regs.

This component is meant to be form of synchronization. Example first reg is connected to first set of ports, writer performs actualizations on first reg and reader reads data from second ram by second set of ports.

Then select is set and access is flipped. Reader now has access to reg 0 and writer to reg 1.

HDL params:

• DATA_WIDTH - default value 32 of type int

• DEFAULT_VAL - default value 0 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• first - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE

• second - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE

• select_sig - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

schematic

__annotations__ = {}

connectReadHwIO(regA, regB)

connectWriteHwIO(regA, regB)