hwtLib.peripheral.uart package

Submodules

hwtLib.peripheral.uart.intf module

class hwtLib.peripheral.uart.intf.IP_Uart[source]

Bases: IntfIpMeta

__annotations__ = {}
__init__()[source]
library
name
vendor
version
class hwtLib.peripheral.uart.intf.Uart(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

Base UART interface, also known as Serial or COM.

HDL IO:

  • rx - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • tx - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_getIpCoreIntfClass()[source]

hwtLib.peripheral.uart.rx module

class hwtLib.peripheral.uart.rx.UartRx(hdlName: str | None = None)[source]

Bases: HwModule

UART Rx channel controller

HDL params:

  • CLK_FREQ - default value 100000000 of type int

  • BAUD - default value 115200 of type int

  • OVERSAMPLING - default value 16 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataOut - of type hwt.hwIOs.std.HwIODataVld - MASTER

  • rxd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

schematic
__annotations__ = {}

hwtLib.peripheral.uart.tx module

class hwtLib.peripheral.uart.tx.UartTx(hdlName: str | None = None)[source]

Bases: HwModule

UART Tx channel controller

HDL params:

  • CLK_FREQ - default value 100000000 of type int

  • BAUD - default value 115200 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

  • txd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}