hwtLib.peripheral.spi package¶

Submodules¶

hwtLib.peripheral.spi.intf module¶

class hwtLib.peripheral.spi.intf.QSPI(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: SpiTristate

SPI interface with 4 tristate data wires

HDL params

SLAVE_CNT - default value 1 of type int
HAS_MISO - default value True of type bool
HAS_MOSI - default value True of type bool
FREQ - default value 100000000 of type int
DATA_WIDTH - default value 4 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - MASTER
io - of type hwt.interfaces.tristate.TristateSig - MASTER
cs - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER

class hwtLib.peripheral.spi.intf.Spi(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Interface

Bare SPI interface (Serial peripheral interface)

HDL params

SLAVE_CNT - default value 1 of type int
HAS_MISO - default value True of type bool
HAS_MOSI - default value True of type bool
FREQ - default value 100000000 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - MASTER
mosi - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
miso - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
cs - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.spi.intf.SpiAgent(sim: HdlSimulator, intf: Spi, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for SPI interface

Variables

~.txData – data to transceiver container
~.rxData – received data
~.chipSelects – values of chip select

chipSelects, rxData and txData are lists of integers

BITS_IN_WORD = 8¶

__init__(sim: HdlSimulator, intf: Spi, allowNoReset=False)[source]¶

Parameters: rst – tuple (rst signal, rst_negated flag)

driverRx()[source]¶

driverTx()[source]¶

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

mergeBits(bits)[source]¶

monitorRx()[source]¶

monitorTx()[source]¶

readRxSig(sig)[source]¶

setEnable(en)[source]¶

splitBits(v)[source]¶

writeTxSig(sig)[source]¶

class hwtLib.peripheral.spi.intf.SpiTristate(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Spi

SPI interface where mosi and miso signal are merged into one tri-state wire

HDL params

SLAVE_CNT - default value 1 of type int
HAS_MISO - default value True of type bool
HAS_MOSI - default value True of type bool
FREQ - default value 100000000 of type int
DATA_WIDTH - default value 1 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - MASTER
io - of type hwt.interfaces.tristate.TristateSig - MASTER
cs - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER

hwtLib.peripheral.spi.master module¶

class hwtLib.peripheral.spi.master.SpiCntrlData(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakedBiDirectional

HandshakedBiDirectional interface with last and slave signal added. If last=1 slave will be deselected and initial slave select wait will be. Slave selects the slave where data should be read from and written to.

HDL params

DATA_WIDTH - default value 64 of type int

HDL IO

slave - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER
din - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE (Master=IN)
dout - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
last - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.spi.master.SpiCntrlDataAgent(sim, intf)[source]¶

Bases: HandshakedBiDirectionalAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.peripheral.spi.master.SpiMaster(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

Master for SPI interface

Variables

~.SPI_FREQ_PESCALER – frequency prescaler to get SPI clk from main clk (Param)
~.SS_WAIT_CLK_TICKS – number of SPI ticks to wait with SPI clk activation after slave select
~.HAS_TX – if set true write part will be instantiated
~.HAS_RX – if set true read part will be instantiated

HDL params

SPI_FREQ_PESCALER - default value 32 of type int
SS_WAIT_CLK_TICKS - default value 4 of type int
HAS_TX - default value True of type bool
HAS_RX - default value True of type bool
SPI_DATA_WIDTH - default value 1 of type int
SLAVE_CNT - default value 1 of type int
HAS_MISO - default value True of type bool
HAS_MOSI - default value True of type bool
FREQ - default value 100000000 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
spi - of type hwtLib.peripheral.spi.intf.Spi - MASTER
data - of type hwtLib.peripheral.spi.master.SpiCntrlData - SLAVE

HDL components

csDecoder - of type hwtLib.logic.binToOneHot.BinToOneHot

schematic

readPart(readTick)[source]¶

spiClkGen(requiresInitWait, en)[source]¶

create clock generator for SPI writeTick is 1 on falling edge of spi clk readTick is 1 on rising edge of spi clk

Returns: tuple of tick signals (if data should be send, if data should be read)

writePart(writeTick, isLastTick, data)[source]¶