hwtLib.xilinx.primitive.examples package

Submodules

hwtLib.xilinx.primitive.examples.dsp48e1Add module

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1Add(hdlName: str | None = None)

Bases: HwModule

__annotations__ = {}

postpone_val(sig_in, clock_enables: List[RtlSignal], name_prefix=None)

Generate a register pipeline which can be used to dealy a value, the length of pipeline is derived from number of clock_enable signals

set_mode(dsp)

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1AluInput(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIORdVldSync

__annotations__ = {}

_initSimAgent(sim: HdlSimulator)

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1AluInputAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)

Bases: HwIODataRdVldAgent

__annotations__ = {}

get_data()

extract data from interface

set_data(data)

write data to interface

hwtLib.xilinx.primitive.examples.dsp48e1Add.generate_handshake_pipe_cntrl(parent: HwModule, n: int, name_prefix: str, in_valid: RtlSignal, out_ready: RtlSignal)

An utility that construct a pipe of registers to store the validity status of a register in the pipeline. These registers are connected in pipeline and synchronized by handshake logic. Clock enable signal for each stage in pipeline is also provided.

Variables:

~.n – number of stages