hwtLib.xilinx.primitive.examples package¶

Submodules¶

hwtLib.xilinx.primitive.examples.dsp48e1Add module¶

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1Add(hdl_name_override: Optional[str] = None)[source]¶

Bases: Unit

postpone_val(sig_in, clock_enables: List[RtlSignal], name_prefix=None)[source]¶: Generate a register pipeline which can be used to dealy a value, the length of pipeline is derived from number of clock_enable signals

set_mode(dsp)[source]¶

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1AluInput(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakeSync

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.xilinx.primitive.examples.dsp48e1Add.Dsp48e1AluInputAG(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

hwtLib.xilinx.primitive.examples.dsp48e1Add.generate_handshake_pipe_cntrl(parent: Unit, n: int, name_prefix: str, in_valid: RtlSignal, out_ready: RtlSignal)[source]¶

An utility that construct a pipe of registers to store the validity status of a register in the pipeline. These registers are connected in pipeline and synchronized by handshake logic. Clock enable signal for each stage in pipeline is also provided.

Variables: ~.n – number of stages