hwtLib.xilinx.primitive package

Subpackages

Submodules

hwtLib.xilinx.primitive.dsp48e1 module

class hwtLib.xilinx.primitive.dsp48e1.DSP48E1(hdlName: str | None = None)[source]

Bases: HwModule

DSP hardblock in Xilinx 7 series (2x pre adder, multiplier, ALU)

_images/xilinx_DSP48E1_basic.png
HDL params:

  • ACASCREG - default value 1 of type int

  • ADREG - default value 1 of type int

  • ALUMODEREG - default value 1 of type int

  • AREG - default value 1 of type int

  • AUTORESET_PATDET - default value NO_RESET of type str

  • A_INPUT - default value DIRECT of type str

  • BCASCREG - default value 1 of type int

  • BREG - default value 1 of type int

  • B_INPUT - default value DIRECT of type str

  • CARRYINREG - default value 1 of type int

  • CARRYINSELREG - default value 1 of type int

  • CREG - default value 1 of type int

  • DREG - default value 1 of type int

  • INMODEREG - default value 1 of type int

  • IS_ALUMODE_INVERTED - default value <HBitsConst b4 0> of type <HBits, 4bits>

  • IS_CARRYIN_INVERTED - default value <HBitsConst b1 0> of type <HBits, 1bit>

  • IS_CLK_INVERTED - default value <HBitsConst b1 0> of type <HBits, 1bit>

  • IS_INMODE_INVERTED - default value <HBitsConst b5 0> of type <HBits, 5bits>

  • IS_OPMODE_INVERTED - default value <HBitsConst b7 0> of type <HBits, 7bits>

  • MASK - default value <HBitsConst b48 70368744177663> of type <HBits, 48bits>

  • MREG - default value 1 of type int

  • OPMODEREG - default value 1 of type int

  • PATTERN - default value <HBitsConst b48 0> of type <HBits, 48bits>

  • PREG - default value 1 of type int

  • SEL_MASK - default value MASK of type str

  • SEL_PATTERN - default value PATTERN of type str

  • USE_DPORT - default value FALSE of type str

  • USE_MULT - default value MULTIPLY of type str

  • USE_PATTERN_DETECT - default value NO_PATDET of type str

  • USE_SIMD - default value ONE48 of type str

HDL IO:

  • CLK - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • A - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 30bits> - SLAVE

  • B - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 18bits> - SLAVE

  • C - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 48bits> - SLAVE

  • D - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 25bits> - SLAVE

  • OPMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 7bits> - SLAVE

  • ALUMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • CECARRYIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CARRYINSEL - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - SLAVE

  • INMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits> - SLAVE

  • CARRYIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • OVERFLOW - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • P - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 48bits> - MASTER

  • PATTERNBDETECT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • PATTERNDETECT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • UNDERFLOW - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • CARRYOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

  • CEA1 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEA2 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEAD - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEB1 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEB2 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEC - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CED - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEM - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEP - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEALUMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CECTRL - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CEINMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTA - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTALLCARRYIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTALUMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTB - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTC - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTCTRL - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTD - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTINMODE - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTM - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • RSTP - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • ACIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 30bits> - SLAVE

  • ACOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 30bits> - MASTER

  • BCIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 18bits> - SLAVE

  • BCOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 18bits> - MASTER

  • CARRYCASCIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • CARRYCASCOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • PCIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 48bits> - SLAVE

  • PCOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 48bits> - MASTER

  • MULTSIGNIN - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • MULTSIGNOUT - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
deassign_xyz_mux()[source]
display_invalid_opmode()[source]
input_check()[source]

hwtLib.xilinx.primitive.dsp48e1_constants module

class hwtLib.xilinx.primitive.dsp48e1_constants.CARRYIN_SEL(*values)[source]

Bases: Enum

A_27_eq_B_17 = 6
CARRYCASCIN = 2
CARRYCASCOUT = 4
CARRYIN = 0
PCIN_47 = 3
PCIN_47_n = 1
P_47 = 7
P_47_n = 5
class hwtLib.xilinx.primitive.dsp48e1_constants.MUL_A_SEL(*values)[source]

Bases: Enum

A1 = 1
A2 = 0
D = 5
D_MINUS_A1 = 9
D_MINUS_A2 = 8
D_PLUS_A1 = 4
D_PLUS_A2 = 3
MINUS_A1 = 7
MINUS_A2 = 6
ZERO = 2
class hwtLib.xilinx.primitive.dsp48e1_constants.MUL_B_SEL(*values)[source]

Bases: Enum

B1 = 1
B2 = 0
class hwtLib.xilinx.primitive.dsp48e1_constants.X_SEL(*values)[source]

Bases: Enum

A_B = 3
M = 5
P = 2
ZERO = 0
class hwtLib.xilinx.primitive.dsp48e1_constants.Y_SEL(*values)[source]

Bases: Enum

C = 12
M = 5
MINUS_1 = 8
ZERO = 0
class hwtLib.xilinx.primitive.dsp48e1_constants.Z_SEL(*values)[source]

Bases: Enum

C = 48
P = 32
PCIN = 16
PCIN_SHIFT_17b = 80
P_MACC = 72
P_SHIFT_17b = 96
ZERO = 0
hwtLib.xilinx.primitive.dsp48e1_constants.get_inmode(AREG: int, USE_DPORT: bool, mul_a_sel: MUL_A_SEL, mul_b_sel: MUL_B_SEL)[source]
hwtLib.xilinx.primitive.dsp48e1_constants.get_opmode(x: X_SEL, y: Y_SEL, z: Z_SEL)[source]

hwtLib.xilinx.primitive.lutAsShiftReg module

class hwtLib.xilinx.primitive.lutAsShiftReg.LutAsShiftReg(hdlName: str | None = None)[source]

Bases: HwModule

This components generates SRL16E and other shift registers.

In order to allow Xilinx Vivado 2020.2 (and possibly any other version) to map this component into SRL16E and equivalents we need to satisfy several conditions: 1. the memory must not have reset 2. the shift expressions must be performed on a single signal 3. whole memory must be single signal 4. the output must be read only by index operator (switch on address does not work) 5. we can not merge memories of individual data bits

__annotations__ = {}

hwtLib.xilinx.primitive.mmcme2 module

class hwtLib.xilinx.primitive.mmcme2.MMCME2_ADV(hdlName: str | None = None)[source]

Bases: HwModule

Mixed-Mode Clock Manager (PLL like frequency synchronizer/clock generator) on Xilinx 7+ series

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

__annotations__ = {}
clkout_duty_chk(CLKOUT_DIVIDE, CLKOUT_DUTY_CYCLE, CLKOUT_DUTY_CYCLE_N)[source]
param_range_chk(para_in, para_name, range_low, range_high)[source]
type_check_bit_param(name)[source]
type_check_bool_param(name)[source]