hwtLib.xilinx.primitive package

Subpackages

• hwtLib.xilinx.primitive.examples package
  • Submodules
  • hwtLib.xilinx.primitive.examples.dsp48e1Add module

Submodules

hwtLib.xilinx.primitive.dsp48e1 module

class hwtLib.xilinx.primitive.dsp48e1.DSP48E1(hdl_name_override: Optional[str] = None)

Bases: Unit

DSP hadblock in Xilinx 7 series (2x pre adder, multiplier, ALU)

See

https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

deassign_xyz_mux()

display_invalid_opmode()

input_check()

hwtLib.xilinx.primitive.dsp48e1_constants module

class hwtLib.xilinx.primitive.dsp48e1_constants.CARRYIN_SEL(value)

Bases: Enum

An enumeration.

A_27_eq_B_17 = 6

CARRYCASCIN = 2

CARRYCASCOUT = 4

CARRYIN = 0

PCIN_47 = 3

PCIN_47_n = 1

P_47 = 7

P_47_n = 5

class hwtLib.xilinx.primitive.dsp48e1_constants.MUL_A_SEL(value)

Bases: Enum

An enumeration.

A1 = 1

A2 = 0

D = 5

D_MINUS_A1 = 9

D_MINUS_A2 = 8

D_PLUS_A1 = 4

D_PLUS_A2 = 3

MINUS_A1 = 7

MINUS_A2 = 6

ZERO = 2

class hwtLib.xilinx.primitive.dsp48e1_constants.MUL_B_SEL(value)

Bases: Enum

An enumeration.

B1 = 1

B2 = 0

class hwtLib.xilinx.primitive.dsp48e1_constants.X_SEL(value)

Bases: Enum

An enumeration.

A_B = 3

M = 5

P = 2

ZERO = 0

class hwtLib.xilinx.primitive.dsp48e1_constants.Y_SEL(value)

Bases: Enum

An enumeration.

C = 12

M = 5

MINUS_1 = 8

ZERO = 0

class hwtLib.xilinx.primitive.dsp48e1_constants.Z_SEL(value)

Bases: Enum

An enumeration.

C = 48

P = 32

PCIN = 16

PCIN_SHIFT_17b = 80

P_MACC = 72

P_SHIFT_17b = 96

ZERO = 0

hwtLib.xilinx.primitive.dsp48e1_constants.get_inmode(AREG: int, USE_DPORT: bool, mul_a_sel: MUL_A_SEL, mul_b_sel: MUL_B_SEL)

hwtLib.xilinx.primitive.dsp48e1_constants.get_opmode(x: X_SEL, y: Y_SEL, z: Z_SEL)

hwtLib.xilinx.primitive.lutAsShiftReg module

class hwtLib.xilinx.primitive.lutAsShiftReg.LutAsShiftReg(hdl_name_override: Optional[str] = None)

Bases: Unit

This components generates SRL16E and other shift registers.

In order to allow Xilinx Vivado 2020.2 (and possibly any other version) to map this component into SRL16E and equivalents we need to satisfy several conditions: 1. the memory must not have reset 2. the shift expressions must be performed on a single signal 3. whole memory must be single signal 4. the output must be read only by index operator (switch on address does not work) 5. we can not merge memories of individual data bits

hwtLib.xilinx.primitive.mmcme2 module

class hwtLib.xilinx.primitive.mmcme2.MMCME2_ADV(hdl_name_override: Optional[str] = None)

Bases: Unit

Mixed-Mode Clock Manager (PLL like frequency synchronizer/clock generator) on Xilinx 7+ series

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

clkout_duty_chk(CLKOUT_DIVIDE, CLKOUT_DUTY_CYCLE, CLKOUT_DUTY_CYCLE_N)

param_range_chk(para_in, para_name, range_low, range_high)

type_check_bit_param(name)

type_check_bool_param(name)