hwtLib.clocking package

Submodules

hwtLib.clocking.clkBuilder module

class hwtLib.clocking.clkBuilder.ClkBuilder(parent, srcInterface, name=None)[source]

Bases: object

Variables:
  • compId – last component id used to avoid name collisions
  • parent – unit in which will be all units created by this builder instantiated
  • name – prefix for all instantiated units
  • end – interface where builder ended
__init__(parent, srcInterface, name=None)[source]
Parameters:
  • parent – unit in which will be all units created by this builder instantiated
  • name – prefix for all instantiated units
  • srcInterface – input clock
edgeDetector(sig, rise=False, fall=False, last=None, initVal=0)[source]
Parameters:
  • sig – signal to detect edges on
  • rise – if True signal for rise detecting will be returned
  • fall – if True signal for fall detecting will be returned
  • last – last value for sig (use f.e. when you have register and it’s next signal (sig=reg.next, last=reg)) if last is None last register will be automatically generated
  • initVal – if last is None initVal will be used as its initialization value
Returns:

signals which is high on on rising/falling edge or both (specified by rise, fall parameter)
oversample(sig, sampleCount, sampleTick, rstSig=None) → Tuple[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal][source]

[TODO] last sample is not sampled correctly

Parameters:
  • sig – signal to oversample
  • sampleCount – count of samples to do
  • sampleTick – signal to enable next sample taking
  • rstSig – rstSig signal to reset internal counter, if is None it is not used
Returns:

typle (oversampled signal, oversample valid signal)
timer(period, enableSig=None, rstSig=None)[source]

Same as timers, just for one

timerDynamic(periodSig, enableSig=None, rstSig=None) → hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]

Same as timer, just period is signal which can be configured dynamically

timers(periods, enableSig=None, rstSig=None)[source]

generate counters specified by count of iterations

Parameters:
  • periods – list of integers/params which specifies periods of timers or tuple (name, integer/param)
  • enableSig – enable signal for all counters
  • rstSig – reset signal for all counters
Attention:

if tick of timer his high and enableSig falls low tick will stay high
Returns:

list of tick signals from timers

hwtLib.clocking.clkDivider module

class hwtLib.clocking.clkDivider.ClkDiv3[source]

Bases: hwt.synthesizer.unit.Unit

Attention:this clock divider implementation suits well for generating of slow output clock inside fpga you should use clocking primitives (http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf)
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)
  • _declr method is called after _config
  • if this object is Unit all interfaces are threaten as externally accessible interfaces if this object is Interface all subinterfaces are loaded
_impl()[source]

implementations

  • implement functionality of design there
  • called after _declr
class hwtLib.clocking.clkDivider.ClkDiv3TC(methodName='runTest')[source]

Bases: hwt.simulator.simTestCase.SimTestCase

test_oscilation()[source]

hwtLib.clocking.timers module

class hwtLib.clocking.timers.DynamicTimerInfo(maxVal, name=None)[source]

Bases: hwtLib.clocking.timers.TimerInfo

Meta informations about timer with dynamic period

__init__(maxVal, name=None)[source]

Initialize self. See help(type(self)) for accurate signature.

static _instantiateTimerTickLogic(timer: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, period: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, enableSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType], rstSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType])[source]

Instantiate incrementing timer with optional reset and enable signal

Parameters:
  • timer – timer main register
  • period – signal with actual period
  • enableSig – optional enable signal for this timer
  • rstSig – optional reset signal for this timer
class hwtLib.clocking.timers.TimerInfo(maxVal, name=None)[source]

Bases: object

Variables:
  • cntrRegister – counter register for this timer
  • tick – signal with tick from this timer
  • parent – parent TimerInfo object from which this timer can be generated
  • maxValOriginal – original value of maxVal
  • maxVal – evaluated value of maxVal
  • name – name prefix which is used for registers and signals for this timer
__init__(maxVal, name=None)[source]

Initialize self. See help(type(self)) for accurate signature.

static _instantiateTimer(parentUnit, timer, enableSig=None, rstSig=None)[source]
Parameters:
  • enableSig – enable signal for all counters
  • rstSig – reset signal for all counters
static _instantiateTimerTickLogic(parentUnit: hwt.synthesizer.unit.Unit, timer: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, origMaxVal: Union[int, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.hdl.value.Value], enableSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType], rstSig: Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, NoneType]) → hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]

Instantiate logic of this timer

Returns:tick signal from this timer
static _instantiateTimerWithParent(parentUnit, timer, parent, enableSig, rstSig)[source]
cntrRegister
static instantiate(parentUnit, timers, enableSig=None, rstSig=None)[source]
Parameters:
  • enableSig – enable signal for all counters
  • rstSig – reset signal for all counters
maxVal
maxValOriginal
name
parent
static resolveSharing(timers)[source]
tick

Module contents