hwtLib.amba.axiLite_comp package

Generic Axi3Lite and Axi4Lite components

note

components from hwtLib.amba.axi_comp can be configured to use Axi4/3Lite interfaces thus this module contains only components unique to Axi3/4Lite iterfaces

Submodules

hwtLib.amba.axiLite_comp.axi4Lite_withId module

class hwtLib.amba.axiLite_comp.axi4Lite_withId.Axi4LiteWithId(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Axi4Lite

Axi4-lite bus interface

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO
AR_CLS

alias of Axi4Lite_addr_withId

AW_CLS

alias of Axi4Lite_addr_withId

B_CLS

alias of Axi4Lite_b_withId

R_CLS

alias of Axi4Lite_r_withId

W_CLS

alias of Axi4Lite_w_withId

_ag: Optional[AgentBase]
_associatedClk: Optional[Interface]
_associatedRst: Optional[Interface]
_ctx: Optional[RtlNetlist]
_direction: INTF_DIRECTION
_hdl_port: Optional[HdlPortItem]
_masterDir: DIRECTION
_name: Optional[str]
_parent: Optional['Unit']
_setAttrListener: Optional[Callable[[str, object], None]]
class hwtLib.amba.axiLite_comp.axi4Lite_withId.Axi4Lite_addr_withId(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Axi4Lite_addr

HDL params

  • ID_WIDTH - default value 0 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO
class hwtLib.amba.axiLite_comp.axi4Lite_withId.Axi4Lite_b_withId(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Axi4Lite_b

HDL params

  • ID_WIDTH - default value 0 of type int

HDL IO
class hwtLib.amba.axiLite_comp.axi4Lite_withId.Axi4Lite_r_withId(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Axi4Lite_r

HDL params

  • ID_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO
class hwtLib.amba.axiLite_comp.axi4Lite_withId.Axi4Lite_w_withId(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Axi4Lite_w

HDL params

  • ID_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO

hwtLib.amba.axiLite_comp.endpoint module

class hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint(structTemplate, intfCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate request from AxiLite interface to fields of structure write has higher priority.

HDL params

  • ADDR_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO

  • clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

  • rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

  • bus - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

  • decoded - of type hwt.interfaces.structIntf.StructIntf with dtype=struct { <Bits, 32bits, unsigned>[4] data0 <Bits, 32bits, unsigned>[4] data1 <Bits, 32bits, unsigned>[2] data2 <Bits, 32bits, unsigned> data3 //<Bits, 32bits, unsigned>[32] empty space struct { <Bits, 16bits, unsigned> data4a <Bits, 16bits, unsigned> data4b <Bits, 32bits, unsigned> data4c } data4 } - MASTER

schematic
__init__(structTemplate, intfCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, shouldEnterFn=None)[source]
Parameters

  • structTemplate – instance of HStruct which describes address space of this endpoint

  • intfCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns

size of one word in unit of address

driveResp(isInAddrRange: Union[RtlSignalBase, HValue], resp: RtlSignalBase)[source]
readPart(awAddr, w_hs)[source]
writePart()[source]
writeRespPart(wAddr, respVld)[source]
hwtLib.amba.axiLite_comp.endpoint._example_AxiLiteEndpoint()[source]

hwtLib.amba.axiLite_comp.to_axi module

class hwtLib.amba.axiLite_comp.to_axi.AxiLite_to_Axi(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]

Bases: BusBridge

Bridge from AxiLite interface to Axi3/4 interface

HDL params

  • INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • DEFAULT_ID - default value 0 of type int

HDL IO
schematic
__init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]
hwtLib.amba.axiLite_comp.to_axi.interface_not_present_on_other(a: Interface, b: Interface)[source]
Returns

set of interfaces which does not have an equivalent on “b”