hwtLib.amba.axiLite_comp.sim package

Submodules

hwtLib.amba.axiLite_comp.sim.mem_space_master module

class hwtLib.amba.axiLite_comp.sim.mem_space_master.AxiLiteMemSpaceMaster(bus, registerMap)[source]

Bases: hwtLib.sim.abstractMemSpaceMaster.AbstractMemSpaceMaster

Controller of AxiLite simulation agent which keeps track of transactions and allows struct like data access

__init__(bus, registerMap)[source]

Initialize self. See help(type(self)) for accurate signature.

_axi3lite_writeAddr(addrChannel, addr, size)[source]

add address transaction to address channel of agent

_axi4lite_writeAddr(addrChannel, addr, size)[source]

add address transaction to address channel of agent

_read(addr, size, onDone=None)[source]

add read address transaction to agent

_write(addr, size, data, mask, onDone=None)[source]

add write address and write data to agent

Parameters

onDone – callback function(sim) -> None

_writeData(data, mask, onDone=None)[source]

add data write transaction to agent

Parameters

onDone – callback function(sim) -> None

class hwtLib.amba.axiLite_comp.sim.mem_space_master.TupleWithCallback(*args)[source]

Bases: tuple

hwtLib.amba.axiLite_comp.sim.ram module

class hwtLib.amba.axiLite_comp.sim.ram.Axi4LiteSimRam(axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None, allow_unaligned_addr=False)[source]

Bases: hwtLib.amba.axi_comp.sim.ram.AxiSimRam

Simulation memory for Axi4Lite interfaces (slave component)

add_r_ag_data(_id, data, isLast)[source]
doWriteAck(_id)[source]
parseReq(req)[source]
pop_w_ag_data(_id)[source]

hwtLib.amba.axiLite_comp.sim.utils module

hwtLib.amba.axiLite_comp.sim.utils.axi_randomize_per_channel(tc: hwt.simulator.simTestCase.SimTestCase, axi)[source]