hwtLib.amba.axiLite_comp.sim package

Submodules

hwtLib.amba.axiLite_comp.sim.memSpaceMaster module

class hwtLib.amba.axiLite_comp.sim.memSpaceMaster.AxiLiteMemSpaceMaster(bus, registerMap)

Bases: AbstractMemSpaceMaster

Controller of AxiLite simulation agent which keeps track of transactions and allows struct like data access

__init__(bus, registerMap)

_axi3lite_writeAddr(addrChannel, addr, size)

add address transaction to address channel of agent

_axi4lite_writeAddr(addrChannel, addr, size)

add address transaction to address channel of agent

_read(addr, size, onDone=None)

add read address transaction to agent

_write(addr, size, data, mask, onDone=None)

add write address and write data to agent

Parameters:

onDone – callback function(sim) -> None

_writeData(data, mask, onDone=None)

add data write transaction to agent

Parameters:

onDone – callback function(sim) -> None

hwtLib.amba.axiLite_comp.sim.ram module

class hwtLib.amba.axiLite_comp.sim.ram.Axi4LiteSimRam(axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None, allow_unaligned_addr=False)

Bases: Axi4SimRam

Simulation memory for Axi4Lite interfaces (slave component)

__annotations__ = {}

add_r_ag_data(_id, data, isLast)

doWriteAck(_id)

parseReq(req)

pop_w_ag_data(_id)

hwtLib.amba.axiLite_comp.sim.utils module

hwtLib.amba.axiLite_comp.sim.utils.axi_randomize_per_channel(tc: SimTestCase, axi)