hwtLib.avalon.sim package

Submodules

hwtLib.avalon.sim.memSpaceMaster module

class hwtLib.avalon.sim.memSpaceMaster.AvalonMmMemSpaceMaster(bus, registerMap)

Bases: AbstractMemSpaceMaster

Controller of AvalonMM simulation agent which keeps track of axi lite transactions and aggregates them to proper register names on target bus

__init__(bus, registerMap)

_read(addr, size, onDone=None)

add read address transaction to agent

_write(addr, size, data, mask, onDone=None)

add write address and write data to agent

Parameters

onDone – callback function(sim) -> None

hwtLib.avalon.sim.ram module

class hwtLib.avalon.sim.ram.AvalonMmSimRam(avalon_mm: AvalonMM, parent=None, clk=None, allow_unaligned_addr=False)

Bases: SimRam

Simulation memory for AvalonMM interfaces (slave component)

__init__(avalon_mm: AvalonMM, parent=None, clk=None, allow_unaligned_addr=False)

Parameters

• clk – clk which should this memory use in simulation (if None the clk associated with an interface is used)

• avalon_mm – avalon_mm (AvalonMM master) interface to listen on

• parent – parent instance of this memory, memory will operate with same memory as parent one

Attention

memories are commiting into memory in “data” property after transaction is complete

_registerOnClock()

_write_single_word(data: HValue, strb: int, word_i: int)

add_r_ag_data(data)

checkRequests()

Check if any request has appeared on interfaces

doRead(addr, size)

doWrite(addr, data_words)

doWriteAck()

parseReq(req)