hwtLib.avalon package¶
This package contains definitions of Avalon interfaces, simulation agents and some componets for mentioned interfaces.
Avalon interfaces were used in many projects around 2015. In 2018 it is still main bus in intel(altera) Quartus (FPGA devel. IDE).
Most commonly used Avalon interfaces are: * AvalonMM (memory mapped) * AvalonST (stream)
Subpackages¶
Submodules¶
hwtLib.avalon.axiToMm module¶
- class hwtLib.avalon.axiToMm.Axi4_to_AvalonMm(hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Bridge from Axi4 interface to Avalon-MM interface
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 512 of type int
ID_WIDTH - default value 4 of type int
RW_PRIORITY - default value READ of type str
R_DATA_FIFO_DEPTH - default value 16 of type int
R_SIZE_FIFO_DEPTH - default value 16 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.avalon.mm.AvalonMM - MASTER
- HDL components
r_size_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
r_data_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
- load_addr_tmp(addr_tmp: StructIntf, axi_addr: Optional[Axi4_addr])[source]¶
- class hwtLib.avalon.axiToMm.IdLenHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
hwtLib.avalon.builder module¶
- class hwtLib.avalon.builder.AvalonMmBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]¶
Bases:
AbstractComponentBuilder
Helper class wich simplifies instantiation and configuration of common components for AvalonMM interfaces
- BuffCls¶
alias of
AvalonMmBuff
- _genericInstance(unit_cls, name, set_params=<function AvalonMmBuilder.<lambda>>, update_params=True, propagate_clk_rst=True)[source]¶
Instantiate generic component and connect basics
- Parameters
unit_cls – class of unit which is being created
name – name for unit_cls instance
set_params – function which updates parameters as is required (parameters are already shared with self.end interface)
hwtLib.avalon.endpoint module¶
- class hwtLib.avalon.endpoint.AvalonMmEndpoint(structTemplate, intfCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)[source]¶
Bases:
BusEndpoint
Delegate request from bus to fields of structure
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 0 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
bus - of type hwtLib.avalon.mm.AvalonMM - SLAVE
decoded - of type hwt.interfaces.structIntf.StructIntf with dtype=struct { <Bits, 32bits, unsigned> field0 <Bits, 32bits, unsigned> field1 <Bits, 32bits, unsigned>[32] bramMapped } - MASTER
- __init__(structTemplate, intfCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)[source]¶
- Parameters
structTemplate – instance of HStruct which describes address space of this endpoint
intfCls – class of bus interface which should be used
shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)
- _getAddrStep()¶
- Returns
how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)
- _getWordAddrStep()¶
- Returns
size of one word in unit of address
hwtLib.avalon.mm module¶
- class hwtLib.avalon.mm.AvalonMM(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
Avalon Memory Mapped interface
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 0 of type int
- HDL IO
read - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
write - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
address - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
waitRequest - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
readData - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
readDataValid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
byteEnable - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
writeData - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
response - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE (Master=IN)
writeResponseValid - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
- class hwtLib.avalon.mm.AvalonMmAddrAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
Bases:
HandshakedAgent
data format is tuple (address, byteEnable, READ/WRITE, burstCount)
two valid signals “read”, “write”
one ready_n signal “waitrequest”)
on write set data and byteenamble as well
- class hwtLib.avalon.mm.AvalonMmAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
Bases:
SyncAgentBase
Simulation agent for AvalonMM bus interface
- Variables
~.req – request data, items are tuples (READ/WRITE, address, burstCount, writeData, writeMask)
~.wResp – write response data
~.rData – data read from interface, items are typles (data, response)
- __init__(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
- Parameters
rst – tuple (rst signal, rst_negated flag)
- getMonitors()[source]¶
Called before simulation to collect all monitors of interfaces from this agent
- property rData¶
- property req¶
- property wResp¶
- class hwtLib.avalon.mm.AvalonMmDataRAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
Bases:
VldSyncedAgent
Simulation/verification agent for data part of AvalomMM interface
vld signal = readDataValid
data signal = (readData, response)
hwtLib.avalon.mmToAxi module¶
- class hwtLib.avalon.mmToAxi.AvalonMm_to_Axi4(hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Convert AvalonMm to AMBA Axi4 interface
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 0 of type int
ID_WIDTH - default value 1 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.avalon.mm.AvalonMM - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER
- HDL components
avmm_buff - of type hwtLib.avalon.mm_buff.AvalonMmBuff
hwtLib.avalon.mm_buff module¶
- class hwtLib.avalon.mm_buff.AvalonMmBuff(hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Transaction buffer for Avalon MM interface
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
MAX_BURST - default value 0 of type int
ADDR_BUFF_DEPTH - default value 4 of type int
DATA_BUFF_DEPTH - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.avalon.mm.AvalonMM - SLAVE
m - of type hwtLib.avalon.mm.AvalonMM - MASTER
- HDL components
r_data - of type hwtLib.handshaked.fifo.HandshakedFifo
w_resp - of type hwtLib.handshaked.fifo.HandshakedFifo
addr - of type hwtLib.handshaked.fifo.HandshakedFifo
- _mk_buff(DEPTH: int, DATA_WIDTH: int) Union[HandshakedFifo, HandshakedReg] [source]¶
hwtLib.avalon.st module¶
- class hwtLib.avalon.st.AvalonST(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Handshaked
Avalon stream interface
- HDL params
DATA_WIDTH - default value 64 of type int
CHANNEL_WIDTH - default value 1 of type int
ERROR_WIDTH - default value 1 of type int
- HDL IO
channel - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER
error - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit, force_vector> - MASTER
data - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
endOfPacket - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
startOfPacket - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
- class hwtLib.avalon.st.AvalonSTAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
HandshakedAgent
Simulation Agent for AvalonST interface Data is stored in .data property and data format is tuple (channel, data, error, startOfPacket, endOfPacket)