hwtLib.avalon package

This package contains definitions of Avalon interfaces, simulation agents and some componets for mentioned interfaces.

Avalon interfaces were used in many projects around 2015. In 2018 it is still main bus in intel(altera) Quartus (FPGA devel. IDE).

Most commonly used Avalon interfaces are: * AvalonMM (memory mapped) * AvalonST (stream)

Subpackages

• hwtLib.avalon.sim package
  • Submodules
  • hwtLib.avalon.sim.memSpaceMaster module
    • AvalonMmMemSpaceMaster
      • AvalonMmMemSpaceMaster.__annotations__
      • AvalonMmMemSpaceMaster.__init__()
      • AvalonMmMemSpaceMaster._read()
      • AvalonMmMemSpaceMaster._write()
  • hwtLib.avalon.sim.ram module
    • AvalonMmSimRam
      • AvalonMmSimRam.__annotations__
      • AvalonMmSimRam.__init__()
      • AvalonMmSimRam._registerOnClock()
      • AvalonMmSimRam._write_single_word()
      • AvalonMmSimRam.add_r_ag_data()
      • AvalonMmSimRam.checkRequests()
      • AvalonMmSimRam.doRead()
      • AvalonMmSimRam.doWrite()
      • AvalonMmSimRam.doWriteAck()
      • AvalonMmSimRam.parseReq()
• hwtLib.avalon.st_comp package
  • Submodules
  • hwtLib.avalon.st_comp.avalonStBuilder module
    • AvalonSTBuilder
      • AvalonSTBuilder.JoinExplicitCls
      • AvalonSTBuilder.JoinFairCls
      • AvalonSTBuilder.JoinPrioritizedCls
      • AvalonSTBuilder.ResizerCls
      • AvalonSTBuilder.SplitFairCls
      • AvalonSTBuilder.SplitPrioritizedCls
      • AvalonSTBuilder.SplitSelectCls
      • AvalonSTBuilder.__annotations__
      • AvalonSTBuilder.castReadyLatencyAndAllowance()
      • AvalonSTBuilder.from_axis()
      • AvalonSTBuilder.to_axis()
  • hwtLib.avalon.st_comp.avalonStLatencyAdapter module
    • AvalonST_latencyAdapter
      • AvalonST_latencyAdapter.__annotations__
      • AvalonST_latencyAdapter._constructAllowanceCreditCounter()
      • AvalonST_latencyAdapter.hwImpl()
  • hwtLib.avalon.st_comp.avalonStToAxi4s module
    • AvalonST_to_Axi4Stream
      • AvalonST_to_Axi4Stream.__annotations__
    • _example_AvalonST_to_Axi4Stream()
  • hwtLib.avalon.st_comp.axi4sToAvalonSt module
    • Axi4Stream_to_AvalonST
      • Axi4Stream_to_AvalonST.__annotations__
    • _example_Axi4Stream_to_AvalonST()

Submodules

hwtLib.avalon.axiToMm module

class hwtLib.avalon.axiToMm.Axi4_to_AvalonMm(hdlName: str | None = None)

Bases: BusBridge

Bridge from Axi4 interface to Avalon-MM interface

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 512 of type int

• waitRequestAllowance - default value 0 of type int

• ID_WIDTH - default value 4 of type int

• RW_PRIORITY - default value READ of type str

• R_DATA_FIFO_DEPTH - default value 16 of type int

• R_SIZE_FIFO_DEPTH - default value 16 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.amba.axi4.Axi4 - SLAVE

• m - of type hwtLib.avalon.mm.AvalonMM - MASTER

HDL components:

• r_size_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo

• r_data_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}

connect_r_fifo(avalon: AvalonMM, axi: Axi4)

load_addr_tmp(addr_tmp: HwIOStruct, axi_addr: Axi4_addr | None)

class hwtLib.avalon.axiToMm.IdLenHs(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIORdVldSync

__annotations__ = {}

hwtLib.avalon.builder module

class hwtLib.avalon.builder.AvalonMmBuilder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)

Bases: AbstractComponentBuilder

Helper class wich simplifies instantiation and configuration of common components for AvalonMM interfaces

BuffCls

alias of AvalonMmBuff

__annotations__ = {}

_genericInstance(hwModuleCls: Type[HwModule], name: str, set_params_fn: Callable[[HwModule], None] | None = None, update_params: bool = True, propagate_clk_rst: bool = True)

Instantiate generic component and connect basics

Parameters:

• hwModuleCls – class of unit which is being created

• name – name for hwModuleCls instance

• set_params_fn – function which updates parameters as is required (parameters are already shared with self.end interface)

buff(addr_items: int = 1, data_items: int = 1)

to_axi(axi_cls: HwIO, id_width: int = 0)

hwtLib.avalon.endpoint module

class hwtLib.avalon.endpoint.AvalonMmEndpoint(structTemplate, hwIOCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 0 of type int

• waitRequestAllowance - default value 0 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• bus - of type hwtLib.avalon.mm.AvalonMM - SLAVE

• decoded - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 32bits, unsigned> field0 <HBits, 32bits, unsigned> field1 <HBits, 32bits, unsigned>[32] bramMapped } - MASTER

schematic

__annotations__ = {}

__init__(structTemplate, hwIOCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)

Parameters:

• structTemplate – instance of HStruct which describes address space of this endpoint

• hwIOCls – class of bus interface which should be used

• shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()

Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()

Returns:

size of one word in unit of address

hwtLib.avalon.endpoint._example_AvalonMmEndpoint()

hwtLib.avalon.mm module

class hwtLib.avalon.mm.AvalonMM(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

Avalon Memory Mapped interface

https://docs.altera.com/r/docs/683091/22.3/avalon-interface-specifications/introduction-to-the-avalon-interface-specifications

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 0 of type int

• waitRequestAllowance - default value 0 of type intworks on same principe as AvalonST.readyAllowance, it specicifies how many transactions may be buffered in destination and thus how many transaction can source send even when ready=0 (waitRequest=1)

HDL IO:

• read - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• write - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• address - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• waitRequest - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• readData - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

• readDataValid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• byteEnable - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

• writeData - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• response - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN (Master=IN)

• writeResponseValid - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}

_getAddrStep()

Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()

Returns:

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)

class hwtLib.avalon.mm.AvalonMmAddrAgent(sim: HdlSimulator, hwIO, allowNoReset=False)

Bases: HwIODataRdVldAgent

data format is tuple (address, byteEnable, READ/WRITE, burstCount)

• two valid signals “read”, “write”

• one ready_n signal “waitrequest”)

• on write set data and byteenamble as well

__annotations__ = {}

__init__(sim: HdlSimulator, hwIO, allowNoReset=False)

Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()

extract data from interface

get_ready()

get value of “ready” signal

classmethod get_ready_signal(hwIO: AvalonMM)

get_valid()

get “valid” signal

classmethod get_valid_signal(hwIO: AvalonMM)

set_data(data)

write data to interface

set_ready(val: int)

set_valid(val: int)

class hwtLib.avalon.mm.AvalonMmAgent(sim: HdlSimulator, hwIO, allowNoReset=False)

Bases: SyncAgentBase

Simulation agent for AvalonMM bus interface

Variables:

• ~.req – request data, items are tuples (READ/WRITE, address, burstCount, writeData, writeMask)

• ~.wResp – write response data

• ~.rData – data read from interface, items are typles (data, response)

__annotations__ = {}

__init__(sim: HdlSimulator, hwIO, allowNoReset=False)

Parameters:

rst – tuple (rst signal, rst_negated flag)

getDrivers()

Note:

use only before running simulator

getMonitors()

Note:

use only before running simulator

property rData

rData_get()

rData_set(v)

property req

req_get()

req_set(v)

setEnable_asDriver(en: bool)

setEnable_asMonitor(en: bool)

property wResp

wResp_get()

wResp_set(v)

class hwtLib.avalon.mm.AvalonMmDataRAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)

Bases: HwIODataVldAgent

Simulation/verification agent for data part of AvalomMM interface

• vld signal = readDataValid

• data signal = (readData, response)

__annotations__ = {}

get_data()

extract data from interface

get_valid()

classmethod get_valid_signal(hwIO)

set_data(data)

write data to interface

set_valid(val)

class hwtLib.avalon.mm.AvalonMmWRespAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)

Bases: HwIODataVldAgent

__annotations__ = {}

get_data()

classmethod get_valid_signal(hwIO)

set_data(data)

hwtLib.avalon.mmToAxi module

class hwtLib.avalon.mmToAxi.AvalonMm_to_Axi4(hdlName: str | None = None)

Bases: BusBridge

Convert AvalonMm to AMBA Axi4 interface

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 0 of type int

• waitRequestAllowance - default value 0 of type int

• ID_WIDTH - default value 1 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.avalon.mm.AvalonMM - SLAVE

• m - of type hwtLib.amba.axi4.Axi4 - MASTER

HDL components:

• avmm_buff - of type hwtLib.avalon.mm_buff.AvalonMmBuff

schematic

__annotations__ = {}

hwtLib.avalon.mm_buff module

class hwtLib.avalon.mm_buff.AvalonMmBuff(hdlName: str | None = None)

Bases: BusBridge

Transaction buffer for Avalon MM interface

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• MAX_BURST - default value 0 of type int

• waitRequestAllowance - default value 0 of type int

• ADDR_BUFF_DEPTH - default value 4 of type int

• DATA_BUFF_DEPTH - default value 4 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.avalon.mm.AvalonMM - SLAVE

• m - of type hwtLib.avalon.mm.AvalonMM - MASTER

HDL components:

• r_data - of type hwtLib.handshaked.fifo.HandshakedFifo

• w_resp - of type hwtLib.handshaked.fifo.HandshakedFifo

• addr - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}

_mk_buff(DEPTH: int, DATA_WIDTH: int) → HandshakedFifo | HandshakedReg

hwtLib.avalon.st module

class hwtLib.avalon.st.AvalonST(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIODataRdVld

Avalon stream interface

Based on Avalon Interface Specifications Updated for Intel Quartus Prime Design Suite: 20.1 https://cdrdv2.intel.com/v1/dl/getContent/667068?fileName=mnl_avalon_spec-683091-667068.pdf

HDL params:

• DATA_WIDTH - default value 64 of type int

• dataBitsPerSymbol - default value 8 of type intsymbol represents minimal unit of transferred data, it is unit for units of “empty” signal

• maxChannel - default value 0 of type int

• readyLatency - default value 0 of type intif 0 the interface works as a typical (AXI4 Stream) ready/valid handshake. if >0 the ready signaling is delayed. The ready cycle is when source received delayed ready=1 from the sink, The source may assert valid only in ready cycle (when it is receiving delayed ready=1)

• readyAllowance - default value None of type Nonedefines how many data can sink capture with ready=False, if it is set to None then readyAllowance=readyLatency

• ERROR_WIDTH - default value 0 of type int

• USE_EMPTY - default value None of type Noneadd “empty” signal which represents the number of symbols that are empty

• SUPPORT_ZLP - default value False of type bool

• packetsPerClock - default value 1 of type int

• firstSymbolInHighOrderBits - default value True of type boolif True the first symbol on msb bits, for False it is on data[dataBitsPerSymbol:0]

HDL IO:

• data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

• empty - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

• startOfPacket - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• endOfPacket - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}

static _getWidthOfEmpty(SEGMENT_DATA_WIDTH: int, BYTE_WIDTH: int, SUPPORT_ZLP: bool)

_getWidthOfEmptyForSelf()

_initSimAgent(sim: HdlSimulator)

class hwtLib.avalon.st.AvalonSTAgent(sim: HdlSimulator, hwIO: AvalonST, allowNoReset=False)

Bases: HwIODataRdVldAgent

Simulation Agent for AvalonST interface Data is stored in .data property and data format is tuple

__annotations__ = {}

__init__(sim: HdlSimulator, hwIO: AvalonST, allowNoReset=False)

Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data() → tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst]

extract data from interface

set_data(data: tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst] | None)

write data to interface

hwtLib.avalon.stSimFrameUtils module

class hwtLib.avalon.stSimFrameUtils.AvalonStSimFrameUtils(SEGMENT_DATA_WIDTH: int, USE_EMPTY: bool, BYTE_WIDTH: int = 8, SEGMENT_CNT: int = 1, SUPPORT_ZLP: bool = False, USE_SOF: bool = True, ERROR_WIDTH: int = 0)

Bases: SimFrameUtils[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst]]

Implementation of SimFrameUtils for AvalonST interface.

__annotations__ = {}

__init__(SEGMENT_DATA_WIDTH: int, USE_EMPTY: bool, BYTE_WIDTH: int = 8, SEGMENT_CNT: int = 1, SUPPORT_ZLP: bool = False, USE_SOF: bool = True, ERROR_WIDTH: int = 0)

__orig_bases__ = (hwtLib.abstract.simFrameUtils.SimFrameUtils[typing.Union[tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst], tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst], tuple[hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst, hwt.hdl.types.bitsConst.HBitsConst]]],)

__parameters__ = ()

concatWordBits(frameBeats: Sequence[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst]])

Convert word tuple (produced by send_bytes() and pack_frame()) to flat HBitsConst (members of input tuple are typically ints so they need to be cast to correct type first)

classmethod from_HwIO(hwio: AvalonST) → Self

Create a an instance of self configured for specified hwio instance

pack_frame(frameVal: HConst | Sequence[int]) → Generator[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst], None, None]

pack data of structure into words of target hwio Words are tuples specific to each hwio.

Parameters:

structVal – value to be send, HConst instance or list of int for each byte

Returns:

generator of word tuples

receive_bytes(ag_data: Deque[tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst, HBitsConst] | tuple[HBitsConst, HBitsConst, HBitsConst]]) → tuple[int, list[int | HBitsConst], bool]

Parameters:

ag_data – list of stream hwio words

Returns:

tuple dataStartOffset, data_Bytes