hwtLib.avalon package

This package contains definitions of Avalon interfaces, simulation agents and some componets for mentioned interfaces.

Avalon interfaces were used in many projects around 2015. In 2018 it is still main bus in intel(altera) Quartus (FPGA devel. IDE).

Most commonly used Avalon interfaces are: * AvalonMM (memory mapped) * AvalonST (stream)

Submodules

hwtLib.avalon.axiToMm module

class hwtLib.avalon.axiToMm.Axi4_to_AvalonMm(hdl_name_override: Optional[str] = None)[source]

Bases: BusBridge

Bridge from Axi4 interface to Avalon-MM interface

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • MAX_BURST - default value 512 of type int

  • ID_WIDTH - default value 4 of type int

  • RW_PRIORITY - default value READ of type str

  • R_DATA_FIFO_DEPTH - default value 16 of type int

  • R_SIZE_FIFO_DEPTH - default value 16 of type int

HDL IO
HDL components
schematic
connect_r_fifo(avalon: AvalonMM, axi: Axi4)[source]
load_addr_tmp(addr_tmp: StructIntf, axi_addr: Optional[Axi4_addr])[source]
class hwtLib.avalon.axiToMm.IdLenHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakeSync

hwtLib.avalon.builder module

class hwtLib.avalon.builder.AvalonMmBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]

Bases: AbstractComponentBuilder

Helper class wich simplifies instantiation and configuration of common components for AvalonMM interfaces

BuffCls

alias of AvalonMmBuff

_genericInstance(unit_cls, name, set_params=<function AvalonMmBuilder.<lambda>>, update_params=True, propagate_clk_rst=True)[source]

Instantiate generic component and connect basics

Parameters
  • unit_cls – class of unit which is being created

  • name – name for unit_cls instance

  • set_params – function which updates parameters as is required (parameters are already shared with self.end interface)

buff(addr_items=1, data_items=1)[source]
to_axi(axi_cls, id_width=0)[source]

hwtLib.avalon.endpoint module

class hwtLib.avalon.endpoint.AvalonMmEndpoint(structTemplate, intfCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • MAX_BURST - default value 0 of type int

HDL IO
schematic
__init__(structTemplate, intfCls=<class 'hwtLib.avalon.mm.AvalonMM'>, shouldEnterFn=None)[source]
Parameters
  • structTemplate – instance of HStruct which describes address space of this endpoint

  • intfCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns

size of one word in unit of address

hwtLib.avalon.endpoint._example_AvalonMmEndpoint()[source]

hwtLib.avalon.mm module

class hwtLib.avalon.mm.AvalonMM(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Interface

Avalon Memory Mapped interface

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • MAX_BURST - default value 0 of type int

HDL IO
_getAddrStep()[source]
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()[source]
Returns

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.avalon.mm.AvalonMmAddrAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]

Bases: HandshakedAgent

data format is tuple (address, byteEnable, READ/WRITE, burstCount)

  • two valid signals “read”, “write”

  • one ready_n signal “waitrequest”)

  • on write set data and byteenamble as well

__init__(sim: HdlSimulator, intf, allowNoReset=False)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

get_ready()[source]

get value of “ready” signal

classmethod get_ready_signal(intf: AvalonMM)[source]
get_valid()[source]

get “valid” signal

classmethod get_valid_signal(intf: AvalonMM)[source]
set_data(data)[source]

write data to interface

set_ready(val: int)[source]
set_valid(val: int)[source]
class hwtLib.avalon.mm.AvalonMmAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]

Bases: SyncAgentBase

Simulation agent for AvalonMM bus interface

Variables
  • ~.req – request data, items are tuples (READ/WRITE, address, burstCount, writeData, writeMask)

  • ~.wResp – write response data

  • ~.rData – data read from interface, items are typles (data, response)

__init__(sim: HdlSimulator, intf, allowNoReset=False)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

property rData
rData_get()[source]
rData_set(v)[source]
property req
req_get()[source]
req_set(v)[source]
setEnable_asDriver(en: bool)[source]
setEnable_asMonitor(en: bool)[source]
property wResp
wResp_get()[source]
wResp_set(v)[source]
class hwtLib.avalon.mm.AvalonMmDataRAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]

Bases: VldSyncedAgent

Simulation/verification agent for data part of AvalomMM interface

  • vld signal = readDataValid

  • data signal = (readData, response)

get_data()[source]

extract data from interface

get_valid()[source]
classmethod get_valid_signal(intf)[source]
set_data(data)[source]

write data to interface

set_valid(val)[source]
class hwtLib.avalon.mm.AvalonMmWRespAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]

Bases: VldSyncedAgent

get_data()[source]
classmethod get_valid_signal(intf)[source]
set_data(data)[source]

hwtLib.avalon.mmToAxi module

class hwtLib.avalon.mmToAxi.AvalonMm_to_Axi4(hdl_name_override: Optional[str] = None)[source]

Bases: BusBridge

Convert AvalonMm to AMBA Axi4 interface

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • MAX_BURST - default value 0 of type int

  • ID_WIDTH - default value 1 of type int

HDL IO
HDL components
schematic

hwtLib.avalon.mm_buff module

class hwtLib.avalon.mm_buff.AvalonMmBuff(hdl_name_override: Optional[str] = None)[source]

Bases: BusBridge

Transaction buffer for Avalon MM interface

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • MAX_BURST - default value 0 of type int

  • ADDR_BUFF_DEPTH - default value 4 of type int

  • DATA_BUFF_DEPTH - default value 4 of type int

HDL IO
HDL components
schematic
_mk_buff(DEPTH: int, DATA_WIDTH: int) Union[HandshakedFifo, HandshakedReg][source]

hwtLib.avalon.st module

class hwtLib.avalon.st.AvalonST(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Handshaked

Avalon stream interface

HDL params
  • DATA_WIDTH - default value 64 of type int

  • CHANNEL_WIDTH - default value 1 of type int

  • ERROR_WIDTH - default value 1 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.avalon.st.AvalonSTAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]

Bases: HandshakedAgent

Simulation Agent for AvalonST interface Data is stored in .data property and data format is tuple (channel, data, error, startOfPacket, endOfPacket)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface