hwtLib.avalon.st_comp package

Submodules

hwtLib.avalon.st_comp.avalonStBuilder module

class hwtLib.avalon.st_comp.avalonStBuilder.AvalonSTBuilder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)[source]

Bases: HsBuilder

JoinExplicitCls = NotImplemented
JoinFairCls = NotImplemented
JoinPrioritizedCls = NotImplemented
ResizerCls = NotImplemented
SplitFairCls = NotImplemented
SplitPrioritizedCls = NotImplemented
SplitSelectCls = NotImplemented
__annotations__ = {}
castReadyLatencyAndAllowance(readyLatency: int, readyAllowance: int | None = None)[source]
classmethod from_axis(parent: HwModule, src: Axi4Stream, name: str | None = None)[source]
to_axis() → Axi4SBuilder[source]

hwtLib.avalon.st_comp.avalonStLatencyAdapter module

class hwtLib.avalon.st_comp.avalonStLatencyAdapter.AvalonST_latencyAdapter(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • DATA_WIDTH - default value 64 of type int

  • dataBitsPerSymbol - default value 8 of type int

  • maxChannel - default value 0 of type int

  • readyLatency - default value 0 of type int

  • readyAllowance - default value None of type None

  • ERROR_WIDTH - default value 0 of type int

  • USE_EMPTY - default value None of type None

  • SUPPORT_ZLP - default value False of type bool

  • packetsPerClock - default value 1 of type int

  • firstSymbolInHighOrderBits - default value True of type bool

  • OUT_readyLatency - default value 0 of type int

  • OUT_readyAllowance - default value None of type None

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.avalon.st.AvalonST - SLAVE

  • dataOut - of type hwtLib.avalon.st.AvalonST - MASTER

schematic
__annotations__ = {}
_constructAllowanceCreditCounter(ready: RtlSignal, valid: RtlSignal, maxVal)[source]
hwImpl() → None[source]

https://cdrdv2.intel.com/v1/dl/getContent/667068?fileName=mnl_avalon_spec-683091-667068.pdf Based on Avalon Interface Specifications Updated for Intel Quartus Prime Design Suite: 20.1 Table 19. Source/Sink Adaptation Requirement

Functionality equivalent to Quartus avst_latency_adapter

Note:

ready cycle is a cycle during which the sink can accept a transfer

Note:

ready is asserted by the sink on cycle <n> to mark cycle <n + readyLatency> as a ready cycle. If readyLatency=0 and readyAllowance=0, data transfers occur only when both ready and valid are asserted. If readyLatency>0 or readyAllowance>0 the source may only assert valid and during ready cycles.

Note:

The sink samples data and on ready cycles where valid is asserted 1.

Note:

if readyLatency==0 the interface works as a typical (AXI4 Stream) ready/valid handshake. if >0 the ready signaling is delayed (inside of the source). The ready cycle is when source received delayed ready=1 from the sink, The source may assert valid only in ready cycle (when it is receiving delayed ready=1)

Note:

if readyLatency > the ready is delayed inside of the source and Avalon-ST itself will use non-delayed value

Note:

readyAllowance defines how many data can sink capture with ready=False, if it is set to None then readyAllowance=readyLatency

Note:

readyLatency/readyAllowance are parameters of FIFO implemented on sink side the “ready” represents “almost-full” of this FIFO, readyLatency=almost-full-remaining-size - 1, readyAllowance=FIFO total size-1. e.g. readyLatency=0, readyAllowance=1 can buffer 1 item with ready=0

Note:

When readyLatency=1 and readyAllowance=2 the dst can accept data 1 cycle after rd=1, and 2 more cycles of transfers are allowed after rd=0.

hwtLib.avalon.st_comp.avalonStToAxi4s module

class hwtLib.avalon.st_comp.avalonStToAxi4s.AvalonST_to_Axi4Stream(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • DATA_WIDTH - default value 64 of type int

  • dataBitsPerSymbol - default value 8 of type int

  • maxChannel - default value 2 of type int

  • readyLatency - default value 0 of type int

  • readyAllowance - default value None of type None

  • ERROR_WIDTH - default value 4 of type int

  • USE_EMPTY - default value True of type bool

  • SUPPORT_ZLP - default value False of type bool

  • packetsPerClock - default value 1 of type int

  • firstSymbolInHighOrderBits - default value True of type bool

HDL IO:
schematic
__annotations__ = {}
hwtLib.avalon.st_comp.avalonStToAxi4s._example_AvalonST_to_Axi4Stream()[source]

hwtLib.avalon.st_comp.axi4sToAvalonSt module

class hwtLib.avalon.st_comp.axi4sToAvalonSt.Axi4Stream_to_AvalonST(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value True of type bool

  • USE_KEEP - default value True of type bool

  • ID_WIDTH - default value 4 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 5 of type int

HDL IO:
HDL components:
schematic
__annotations__ = {}
hwtLib.avalon.st_comp.axi4sToAvalonSt._example_Axi4Stream_to_AvalonST()[source]