hwtLib.clocking package

A package dedicated to a component and utilities related to clock generation and transformation as well as other functionality related to time based syncrhonization.

Submodules

hwtLib.clocking.cdc module

class hwtLib.clocking.cdc.Cdc(hdlName: str | None = None)

Bases: HwModule

CDC (Clock Domain Crossing) for HwIOSignal interface (Synchronizes the signal for different clock domain.)

Variables:

• ~.DATA_WIDTH – width of data-signal

• ~.INIT_VAL – initialization value for registers

• ~.IN_FREQ – frequency of clock signal for input data [Hz]

• ~.OUT_FREQ – frequency of clock signal for output data [Hz]

• ~.OUT_REG_CNT – number of registers for synchronization in dataOut clock domain

HDL params:

• DATA_WIDTH - default value 1 of type int

• INIT_VAL - default value 0 of type int

• IN_FREQ - default value 100000000.0 of type float

• OUT_FREQ - default value 100000000.0 of type float

• OUT_REG_CNT - default value 2 of type int

HDL IO:

• dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataIn_rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataOut_rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.clocking.cdc.CdcPulseGen(hdlName: str | None = None)

Bases: Cdc

if inData_clk.FREQ > outData_clk.FREQ:
    outData_clk.FREQ >= 1.5*inData_clk.FREQ
else:
    inData_clk.FREQ >= 1.5*outData_clk.FREQ

HDL params:

• DATA_WIDTH - default value 1 of type int

• INIT_VAL - default value 0 of type int

• IN_FREQ - default value 100000000.0 of type float

• OUT_FREQ - default value 100000000.0 of type float

• OUT_REG_CNT - default value 3 of type int

HDL IO:

• dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataIn_rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

• dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataOut_rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

• dataOut_en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

class hwtLib.clocking.cdc.SignalCdcBuilder(sig, in_clk_rst: Tuple[RtlSignal, RtlSignal], out_clk_rst: Tuple[RtlSignal, RtlSignal], reg_init_val, name_prefix: str | None = None)

Bases: object

Object which can build CDCs for simple HwIOSignal interfaces. It automatically adding constrains and check correnctnes of CDC path. Main purpose of this class is to allow building of CDCs without requirement of component instantiation.

__init__(sig, in_clk_rst: Tuple[RtlSignal, RtlSignal], out_clk_rst: Tuple[RtlSignal, RtlSignal], reg_init_val, name_prefix: str | None = None)

Parameters:

• sig – data in signal

• in_clk_rst – tuple source clk signal, rst signal

• out_clk_rst – tuple destination clk signal, rst signal

• reg_init_val – register reset value

Note:

rst/rst_n is automatically resolved from reset type

_parent()

_reg(name, clk_rst)

add_in_reg()

add_out_reg(en: RtlSignal | None = None)

hwtLib.clocking.clkBuilder module

class hwtLib.clocking.clkBuilder.ClkBuilder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)

Bases: AbstractComponentBuilder

Helper object which simplifies construction of the oversampling, shared timers, edge detector, … logic

__annotations__ = {}

edgeDetector(sig: RtlSignal | HwIO, rise: bool = False, fall: bool = False, last: RtlSignal | HwIO | None = None, initVal=0)

Parameters:

• sig – signal to detect edges on

• rise – if True signal for rise detecting will be returned

• fall – if True signal for fall detecting will be returned

• last – last value for sig (use e.g. when you have register and it’s next signal (sig=reg._rtlNextSig, last=reg)) if last is None last register will be automatically generated

• initVal – if last is None initVal will be used as its initialization value

Returns:

signals which is high on on rising/falling edge or both (specified by rise, fall parameter)

oversample(sig: RtlSignal | HwIO, sampleCount: int, sampleTick: RtlSignal | HwIO, rstSig: RtlSignal | HwIO | None = None) → Tuple[RtlSignal, RtlSignal]

[TODO] last sample is not sampled correctly

Parameters:

• sig – signal to oversample

• sampleCount – count of samples to do

• sampleTick – signal to enable next sample taking

• rstSig – rstSig signal to reset internal counter, if is None it is not used

Returns:

typle (oversampled signal, oversample valid signal)

regPipe(din: RtlSignal | HwIO, number_of_regs: int, name: str | None = None, def_val: Sequence | None = None) → list[RtlSignal | HwIO]

Instantiate path of registers used to delay the signal or to filter IO

Returns:

the list of newly created registers and din as a first item

timer(period: int | Tuple[str, int], enableSig: RtlSignal | HwIO | None = None, rstSig: RtlSignal | HwIO | None = None)

Same as ClkBuilder.timers(), just for single timer intance

timerDynamic(periodSig, enableSig: RtlSignal | HwIO | None = None, rstSig: RtlSignal | HwIO | None = None) → RtlSignal

Same as timer, just period is signal which can be configured dynamically

timers(periods: List[int | Tuple[str, int]], enableSig=None, rstSig=None)

generate counters specified by count of iterations

Parameters:

• periods – list tick period or tuple (name, period) for timer, period is specified in the number of clk ticks

• enableSig – enable signal for all counters

• rstSig – reset signal for all counters

Attention:

if tick of timer his high and enableSig falls low tick will stay high

Returns:

list of tick signals from timers

hwtLib.clocking.timers module

class hwtLib.clocking.timers.DynamicTimerInfo(maxVal, name=None)

Bases: TimerInfo

Meta informations about timer with dynamic period

Note:

See TimerInfo

__init__(maxVal, name=None)

static _instantiateTimerTickLogic(timer: RtlSignal, period: RtlSignal, enableSig: RtlSignal | None, rstSig: RtlSignal | None)

Instantiate incrementing timer with optional reset and enable signal

Parameters:

• timer – timer main register

• period – signal with actual period

• enableSig – optional enable signal for this timer

• rstSig – optional reset signal for this timer

cntrRegister

maxVal

maxValOriginal

name

parent

tick

class hwtLib.clocking.timers.TimerInfo(maxVal, name=None)

Bases: object

Generator of varius shared timers. Use this from hwtLib.clocking.clkBuilder.ClkBuilder

Variables:

• ~.cntrRegister – counter register for this timer

• ~.tick – signal with tick from this timer

• ~.parent – parent TimerInfo object from which this timer can be generated

• ~.maxValOriginal – original value of maxVal

• ~.maxVal – evaluated value of maxVal

• ~.name – name prefix which is used for registers and signals for this timer

__annotations__ = {}

__init__(maxVal, name=None)

__repr__()

Return repr(self).

__slots__ = ['maxVal', 'maxValOriginal', 'parent', 'cntrRegister', 'tick', 'name']

static _instantiateTimer(parentHwModule, timer, enableSig=None, rstSig=None)

Parameters:

• enableSig – enable signal for all counters

• rstSig – reset signal for all counters

static _instantiateTimerTickLogic(parentHwModule: HwModule, timer: RtlSignal, origMaxVal: int | RtlSignal | HConst, enableSig: RtlSignal | None, rstSig: RtlSignal | None) → RtlSignal

Instantiate logic of this timer

Returns:

tick signal from this timer

static _instantiateTimerWithParent(parentHwModule: HwModule, timer, parent, enableSig, rstSig)

cntrRegister

static instantiate(parentHwModule, timers, enableSig=None, rstSig=None)

Parameters:

• enableSig – enable signal for all counters

• rstSig – reset signal for all counters

maxVal

maxValOriginal

name

parent

static resolveSharing(timers)

tick

hwtLib.clocking.vldSynced_cdc module

class hwtLib.clocking.vldSynced_cdc.VldSyncedCdc(hwIOCls: Type[HwIODataVld])

Bases: HwModule

Clock Domain Crossing for HwIODataVld interfaces

HDL params:

• HWIO_CLS - default value <class ‘hwt.hwIOs.std.HwIODataVld’> of type type

• DATA_WIDTH - default value 64 of type int

• DATA_RESET_VAL - default value None of type None

• IN_FREQ - default value 100000000 of type int

• OUT_FREQ - default value 100000000 of type int

• IGNORE_DATA_LOSE - default value False of type bool

HDL IO:

• dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• dataIn - of type hwt.hwIOs.std.HwIODataVld - SLAVE

• dataOut - of type hwt.hwIOs.std.HwIODataVld - MASTER

schematic

__annotations__ = {}

__init__(hwIOCls: Type[HwIODataVld])

Parameters:

hshwIO – class of interface which should be used as interface of this unit

get_data(hwIO)

classmethod get_valid_signal(hwIO)

hwtLib.clocking.vldSynced_cdc._example_VldSyncedCdc()