hwtLib.clocking package

A package dedicated to a component and utilities related to clock generation and transformation as well as other functionality related to time based syncrhonization.

Submodules

hwtLib.clocking.cdc module

class hwtLib.clocking.cdc.Cdc(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

CDC (Clock Domain Crossing) for Signal interface (Synchronizes the signal for different clock domain.)

Variables

  • ~.DATA_WIDTH – width of data-signal

  • ~.INIT_VAL – initialization value for registers

  • ~.IN_FREQ – frequency of clock signal for input data [Hz]

  • ~.OUT_FREQ – frequency of clock signal for output data [Hz]

  • ~.OUT_REG_CNT – number of registers for synchronization in dataOut clock domain

HDL params

  • DATA_WIDTH - default value 1 of type int

  • INIT_VAL - default value 0 of type int

  • IN_FREQ - default value 100000000.0 of type float

  • OUT_FREQ - default value 100000000.0 of type float

  • OUT_REG_CNT - default value 2 of type int

HDL IO
schematic
class hwtLib.clocking.cdc.CdcPulseGen(hdl_name_override: Optional[str] = None)[source]

Bases: Cdc

if inData_clk.FREQ > outData_clk.FREQ:
    outData_clk.FREQ >= 1.5*inData_clk.FREQ
else:
    inData_clk.FREQ >= 1.5*outData_clk.FREQ
HDL params

  • DATA_WIDTH - default value 1 of type int

  • INIT_VAL - default value 0 of type int

  • IN_FREQ - default value 100000000.0 of type float

  • OUT_FREQ - default value 100000000.0 of type float

  • OUT_REG_CNT - default value 3 of type int

HDL IO
schematic
class hwtLib.clocking.cdc.SignalCdcBuilder(sig, in_clk_rst: Tuple[RtlSignal, RtlSignal], out_clk_rst: Tuple[RtlSignal, RtlSignal], reg_init_val, name_prefix: Optional[str] = None)[source]

Bases: object

Object which can build CDCs for simple Signal interfaces. It automatically adding constrains and check correnctnes of CDC path. Main purpose of this class is to allow building of CDCs without requirement of component instantiation.

__init__(sig, in_clk_rst: Tuple[RtlSignal, RtlSignal], out_clk_rst: Tuple[RtlSignal, RtlSignal], reg_init_val, name_prefix: Optional[str] = None)[source]
Parameters

  • sig – data in signal

  • in_clk_rst – tuple source clk signal, rst signal

  • out_clk_rst – tuple destination clk signal, rst signal

  • reg_init_val – register reset value

Note

rst/rst_n is automatically resolved from reset type

_parent()[source]
_reg(name, clk_rst)[source]
add_in_reg()[source]
add_out_reg(en: Optional[RtlSignal] = None)[source]

hwtLib.clocking.clkBuilder module

class hwtLib.clocking.clkBuilder.ClkBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]

Bases: AbstractComponentBuilder

Helper object which simplifies construction of the oversampling, shared timers, edge detector, … logic

Variables

  • ~.compId – last component id used to avoid name collisions

  • ~.parent – unit in which will be all units created by this builder instantiated

  • ~.name – prefix for all instantiated units

  • ~.end – interface where builder ended

edgeDetector(sig, rise=False, fall=False, last=None, initVal=0)[source]
Parameters

  • sig – signal to detect edges on

  • rise – if True signal for rise detecting will be returned

  • fall – if True signal for fall detecting will be returned

  • last – last value for sig (use e.g. when you have register and it’s next signal (sig=reg.next, last=reg)) if last is None last register will be automatically generated

  • initVal – if last is None initVal will be used as its initialization value

Returns

signals which is high on on rising/falling edge or both (specified by rise, fall parameter)

oversample(sig, sampleCount, sampleTick, rstSig=None) → Tuple[RtlSignal, RtlSignal][source]

[TODO] last sample is not sampled correctly

Parameters

  • sig – signal to oversample

  • sampleCount – count of samples to do

  • sampleTick – signal to enable next sample taking

  • rstSig – rstSig signal to reset internal counter, if is None it is not used

Returns

typle (oversampled signal, oversample valid signal)

reg_path(din, number_of_regs, name=None, def_val=None)[source]

Instantiate path of registers used to delay the signal or to filter IO

Returns

the last register in path

timer(period, enableSig=None, rstSig=None)[source]

Same as ClkBuilder.timers(), just for single timer intance

timerDynamic(periodSig, enableSig=None, rstSig=None) → RtlSignal[source]

Same as timer, just period is signal which can be configured dynamically

timers(periods: List[Union[int, Tuple[str, int]]], enableSig=None, rstSig=None)[source]

generate counters specified by count of iterations

Parameters

  • periods – list tick period or tuple (name, period) for timer, period is specified in the number of clk ticks

  • enableSig – enable signal for all counters

  • rstSig – reset signal for all counters

Attention

if tick of timer his high and enableSig falls low tick will stay high

Returns

list of tick signals from timers

hwtLib.clocking.timers module

class hwtLib.clocking.timers.DynamicTimerInfo(maxVal, name=None)[source]

Bases: TimerInfo

Meta informations about timer with dynamic period

Note

See TimerInfo

__init__(maxVal, name=None)[source]
static _instantiateTimerTickLogic(timer: RtlSignal, period: RtlSignal, enableSig: Optional[RtlSignal], rstSig: Optional[RtlSignal])[source]

Instantiate incrementing timer with optional reset and enable signal

Parameters

  • timer – timer main register

  • period – signal with actual period

  • enableSig – optional enable signal for this timer

  • rstSig – optional reset signal for this timer

cntrRegister
maxVal
maxValOriginal
name
parent
tick
class hwtLib.clocking.timers.TimerInfo(maxVal, name=None)[source]

Bases: object

Generator of varius shared timers. Use this from hwtLib.clocking.clkBuilder.ClkBuilder

Variables

  • ~.cntrRegister – counter register for this timer

  • ~.tick – signal with tick from this timer

  • ~.parent – parent TimerInfo object from which this timer can be generated

  • ~.maxValOriginal – original value of maxVal

  • ~.maxVal – evaluated value of maxVal

  • ~.name – name prefix which is used for registers and signals for this timer

__init__(maxVal, name=None)[source]
__repr__()[source]

Return repr(self).

__slots__ = ['maxVal', 'maxValOriginal', 'parent', 'cntrRegister', 'tick', 'name']
static _instantiateTimer(parentUnit, timer, enableSig=None, rstSig=None)[source]
Parameters

  • enableSig – enable signal for all counters

  • rstSig – reset signal for all counters

static _instantiateTimerTickLogic(parentUnit: Unit, timer: RtlSignal, origMaxVal: Union[int, RtlSignal, HValue], enableSig: Optional[RtlSignal], rstSig: Optional[RtlSignal]) → RtlSignal[source]

Instantiate logic of this timer

Returns

tick signal from this timer

static _instantiateTimerWithParent(parentUnit, timer, parent, enableSig, rstSig)[source]
cntrRegister
static instantiate(parentUnit, timers, enableSig=None, rstSig=None)[source]
Parameters

  • enableSig – enable signal for all counters

  • rstSig – reset signal for all counters

maxVal
maxValOriginal
name
parent
static resolveSharing(timers)[source]
tick

hwtLib.clocking.vldSynced_cdc module

class hwtLib.clocking.vldSynced_cdc.VldSyncedCdc(intfCls: Type[VldSynced])[source]

Bases: Unit

Clock Domain Crossing for VldSynced interfaces

HDL params

  • INTF_CLS - default value <class ‘hwt.interfaces.std.VldSynced’> of type type

  • DATA_WIDTH - default value 64 of type int

  • DATA_RESET_VAL - default value None of type None

  • IN_FREQ - default value 100000000 of type int

  • OUT_FREQ - default value 100000000 of type int

  • IGNORE_DATA_LOSE - default value False of type bool

HDL IO
schematic
__init__(intfCls: Type[VldSynced])[source]
Parameters

hsIntfCls – class of interface which should be used as interface of this unit

get_data(intf)[source]
classmethod get_valid_signal(intf)[source]
hwtLib.clocking.vldSynced_cdc._example_VldSyncedCdc()[source]