hwtLib.commonHwIO package¶

A package dedicated to commonly used interfaces wich are not part of any standard. This usually involves trivial interfaces which do have some well defined meaning.

Submodules¶

hwtLib.commonHwIO.addr module¶

class hwtLib.commonHwIO.addr.HwIOAddrRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIORdVldSync

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr.HwIOAddrRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

hwtLib.commonHwIO.addr_data module¶

class hwtLib.commonHwIO.addr_data.HwIOAddrData(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL params:

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int

HDL IO:

addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN (Master=IN)

__annotations__ = {}¶

class hwtLib.commonHwIO.addr_data.HwIOAddrDataBitMaskRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIOAddrDataRdVld

HDL params:

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO:

vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
mask - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr_data.HwIOAddrDataMaskRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.commonHwIO.addr_data.HwIOAddrDataRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIORdVldSync

Simple handshaked interface with address and data signal

HDL params:

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO:

vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr_data.HwIOAddrDataRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.commonHwIO.addr_data.HwIOAddrDataVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.commonHwIO.addr_data.HwIOAddrDataVldRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIOAddrDataRdVld

HDL params:

ADDR_WIDTH - default value 8 of type int
DATA_WIDTH - default value 8 of type int
HAS_MASK - default value False of type bool

HDL IO:

vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
vld_flag - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.commonHwIO.addr_data_bidir module¶

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrInDataOutRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIORdVldSyncBiDirectionalData

HDL params:

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO:

addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrInDataOutRdVldAgent(sim, hwIO)[source]¶

Bases: HwIORdVldSyncBiDirectionalDataAgent

Simulation agent for AddrDataOutInHs interface

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrInOutDataInRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIORdVldSyncBiDirectionalData

HDL params:

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO:

addrIn - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)
addrOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrInOutDataInRdVldAgent(sim, hwIO)[source]¶

Bases: HwIORdVldSyncBiDirectionalDataAgent

Simulation agent for HwIOAddrInOutDataInRdVld interface

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrOutDataInRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIORdVldSyncBiDirectionalData

HDL params:

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int

HDL IO:

addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN
data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.addr_data_bidir.HwIOAddrOutDataInRdVldAgent(sim, hwIO)[source]¶

Bases: HwIORdVldSyncBiDirectionalDataAgent

Simulation agent for HwIOAddrOutDataInRdVld interface

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data)[source]¶: write data to interface

hwtLib.commonHwIO.addr_data_to_Axi module¶

class hwtLib.commonHwIO.addr_data_to_Axi.AddrDataRdVld_to_Axi(hwIOCls=<class 'hwtLib.amba.axi4.Axi4'>, hdlName: str | None = None)[source]¶

Bases: BusBridge

Bridge HwIOAddrDataRdVld,HwIORamRdVldR -> Axi3/4

read delay: 1, transaction overlap 0
write delay: 1, transaction overlap 0

Variables:

~.S_ADDR_STEP – number of bites per step on HwIOAddrDataRdVld,HwIORamRdVldR interfaces
~.M_DATA_WIDTH – data width for AXI interface
~.M_ID_WIDTH – id width for AXI interface
~.M_ADDR_OFFSET – address offset value for axi interface

HDL params:

ADDR_WIDTH - default value 16 of type int
DATA_WIDTH - default value 32 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
S_ADDR_STEP - default value 16 of type int
S_ADDR_WIDTH - default value 15 of type int
S_DATA_WIDTH - default value 16 of type int
M_ADDR_OFFSET - default value 0 of type int
MAX_TRANS_OVERLAP - default value 64 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
s_r - of type hwtLib.handshaked.ramAsAddrDataRdVld.HwIORamRdVldR - SLAVE
s_w - of type hwtLib.commonHwIO.addr_data.HwIOAddrDataRdVld - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER

HDL components:

axi_buff - of type hwtLib.amba.axi_comp.buff.AxiBuff
gen_r_tmp_parser_0 - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
gen__select_fifo_0 - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinPrioritized.HsJoinPrioritized
deparsed_deparser_0 - of type hwtLib.amba.axis_comp.frame_deparser._deparser.Axi4S_frameDeparser
w_data_reg - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__annotations__ = {}¶

__init__(hwIOCls=<class 'hwtLib.amba.axi4.Axi4'>, hdlName: str | None = None)[source]¶

addr_defaults(a: Axi4_addr)[source]¶

connect_addr(src, dst)[source]¶

connect_r(s_r: HwIORamRdVldR, axi: Axi4, r_cntr: RtlSignal, CNTR_MAX: int, in_axi_t: HStruct | HUnion)[source]¶

connect_w(s_w: HwIOAddrDataRdVld, axi: Axi4, w_cntr: RtlSignal, CNTR_MAX: int, in_axi_t: HStruct)[source]¶

generate_in_axi_type()[source]¶

split_subaddr(addr: RtlSignal)[source]¶

hwtLib.commonHwIO.addr_data_to_Axi.example_AddrDataRdVld_to_Axi()[source]¶: Download a 512b word over 64b interface

hwtLib.commonHwIO.data_mask_last_hs module¶

class hwtLib.commonHwIO.data_mask_last_hs.HwIODataMaskLastRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataRdVld

HwIODataRdVld interface with data, mask, last signal.

HDL params:

MASK_GRANULARITY - default value 8 of type int
DATA_WIDTH - default value 64 of type int

HDL IO:

data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
mask - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.data_mask_last_hs.HwIODataMaskRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

Simulation agent for HwIODataMaskLastRdVld interface.

__annotations__ = {}¶

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

hwtLib.commonHwIO.index_key_hs module¶

class hwtLib.commonHwIO.index_key_hs.HwIOIndexKeyInRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataRdVld

HDL params:

INDEX_WIDTH - default value 4 of type int
KEY_WIDTH - default value 4 of type int

HDL IO:

vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
key - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN (Master=IN)
index - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.index_key_hs.HwIOIndexKeyInRdVldAgent(sim, hwIO)[source]¶

Bases: HwIORdVldSyncBiDirectionalDataAgent

__annotations__ = {}¶

get_data() → Tuple[int, int] | int[source]¶: extract data from interface

onDriverWriteAck()[source]¶: read din

onMonitorReady()[source]¶: write din

set_data(data: Tuple[int, int] | int)[source]¶: write data to interface

class hwtLib.commonHwIO.index_key_hs.HwIOIndexKeyRdVld(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataRdVld

HDL params:

INDEX_WIDTH - default value 4 of type int
KEY_WIDTH - default value 4 of type int

HDL IO:

vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
key - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
index - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.commonHwIO.index_key_hs.HwIOIndexKeyRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

__annotations__ = {}¶

get_data() → Tuple[int, int] | int[source]¶: extract data from interface

set_data(data: Tuple[int, int] | int)[source]¶: write data to interface