hwtLib.cesnet.mi32 package

Mi32 is simple bus interfaces commonly used as a service bus. This package contains various components and utilities for this interface.

Submodules

hwtLib.cesnet.mi32.axi4Lite_to_mi32 module

class hwtLib.cesnet.mi32.axi4Lite_to_mi32.Axi4Lite_to_Mi32(hdlName: str | None = None)[source]

Bases: BusBridge

Bridge from AxiLite interface to MI32 interface

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

  • RW_PRIORITY - default value READ of type str

HDL IO:
schematic
__annotations__ = {}

hwtLib.cesnet.mi32.buff module

class hwtLib.cesnet.mi32.buff.Mi32AddrHs(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

Equivalent of Mi32 address/write data channel with HwIORdVldSync compatible signal names

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • read - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • write - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • be - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • dwr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}
class hwtLib.cesnet.mi32.buff.Mi32Buff(hdlName: str | None = None)[source]

Bases: BusBridge

Buffer for Mi32 interface

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

  • ADDR_BUFF_DEPTH - default value 1 of type int

  • DATA_BUFF_DEPTH - default value 1 of type int

HDL IO:
HDL components:
schematic
_Mi32_addr_to_Mi32AddrHs(mi32: Mi32, tmp_name)[source]
__annotations__ = {}
_connect_Mi32AddrHs_to_Mi32(mi32ahs: Mi32AddrHs, mi32: Mi32)[source]

hwtLib.cesnet.mi32.builder module

class hwtLib.cesnet.mi32.builder.Mi32Builder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)[source]

Bases: AxiBuilder

BuffCdcCls = NotImplemented
BuffCls

alias of _Mi32Buff

__annotations__ = {}
classmethod from_axi(parent, axi, name=None)[source]

converter AXI/AxiLite -> Mi32

sliding_window(window_size: int, new_addr_width: int)[source]

Instantiate a sliding window with an offset register which allows to virtually extend the addressable memory space

to_axi(axi_cls)[source]

converter Mi32 -> AXI/AXILite

class hwtLib.cesnet.mi32.builder._Mi32Buff(hwIOCls, hdlName: str | None = None)[source]

Bases: Mi32Buff

Mi32Buff constructor which ignores interface in constructor

__annotations__ = {}
__init__(hwIOCls, hdlName: str | None = None)[source]

hwtLib.cesnet.mi32.endpoint module

class hwtLib.cesnet.mi32.endpoint.Mi32Endpoint(structTemplate, hwIOCls=<class 'hwtLib.cesnet.mi32.intf.Mi32'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • bus - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE

  • decoded - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 32bits, unsigned> field0 <HBits, 32bits, unsigned> field1 } - MASTER

schematic
__annotations__ = {}
__init__(structTemplate, hwIOCls=<class 'hwtLib.cesnet.mi32.intf.Mi32'>, shouldEnterFn=None)[source]
Parameters:

  • structTemplate – instance of HStruct which describes address space of this endpoint

  • hwIOCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns:

size of one word in unit of address

hwtLib.cesnet.mi32.endpoint._example_Mi32Endpoint()[source]

hwtLib.cesnet.mi32.interconnectMatrix module

class hwtLib.cesnet.mi32.interconnectMatrix.Mi32InterconnectMatrix(hdlName: str | None = None)[source]

Bases: BusInterconnect

Simple matrix interconnect for Mi32 interface

HDL params:

  • SLAVES - default value ((0, 256), (256, 256), (<class ‘hwtLib.abstract.busInterconnect.AUTO_ADDR’>, 256), (4096, 4096)) of type tuple

  • MASTERS - default value ({0, 1, 2, 3},) of type tuple

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

  • MAX_TRANS_OVERLAP - default value 4 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
hwtLib.cesnet.mi32.interconnectMatrix._example_Mi32InterconnectMatrix()[source]

hwtLib.cesnet.mi32.intf module

class hwtLib.cesnet.mi32.intf.Mi32(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

Simple memory interface similar to AvalonMM

Variables:

  • ~.addr – r/w address

  • ~.rd – read enable

  • ~.wr – write enable

  • ~.ardy – slave address channel ready

  • ~.be – data byte mask for write

  • ~.dwr – write data

  • ~.drd – read data

  • ~.drdy – read data valid

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • wr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • ardy - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • be - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

  • dwr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • drd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

  • drdy - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}
_getAddrStep()[source]
Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()[source]
Returns:

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.cesnet.mi32.intf.Mi32AddrAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]

Bases: HwIODataRdVldAgent

Variables:

~.requests – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)

Note:

two valid signals “read”, “write”

Note:

one ready_n signal “waitrequest”

Note:

on write set data and byteenamble as well

__annotations__ = {}
get_data()[source]

extract data from interface

classmethod get_ready_signal(hwIO)[source]
get_valid()[source]

get “valid” signal

classmethod get_valid_signal(hwIO)[source]
set_data(data)[source]

write data to interface

set_valid(val)[source]
class hwtLib.cesnet.mi32.intf.Mi32Agent(sim: HdlSimulator, hwIO: Mi32, allowNoReset=False)[source]

Bases: SyncAgentBase

Simulation agent for Mi32 bus interface

Variables:

  • ~.requests – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)

  • ~.rData – data read from interface

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: Mi32, allowNoReset=False)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

getDrivers()[source]
Note:

use only before running simulator

getMonitors()[source]
Note:

use only before running simulator

property r_data
r_data_get()[source]
r_data_set(v)[source]
property requests
requests_get()[source]
requests_set(v)[source]
class hwtLib.cesnet.mi32.intf.Mi32DataAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]

Bases: HwIODataVldAgent

__annotations__ = {}
get_data()[source]
classmethod get_valid_signal(hwIO: Mi32)[source]
set_data(data)[source]

hwtLib.cesnet.mi32.mi32SimMemSpaceMaster module

class hwtLib.cesnet.mi32.mi32SimMemSpaceMaster.Mi32SimMemSpaceMaster(bus, registerMap)[source]

Bases: AbstractMemSpaceMaster

Controller of BramPort simulation agent which keeps track of transactions and allows struct like data access

Variables:

~.req – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)

__annotations__ = {}
_read(addr, size, onDone)[source]

Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)[source]

Add write transaction to agent of interface

Parameters:

  • addr – address value on bus to write on

  • size – size of data to write in bites

  • data – data to write on bus

  • onDone – on write done callback function(sim) -> None

hwtLib.cesnet.mi32.sim_ram module

class hwtLib.cesnet.mi32.sim_ram.Mi32SimRam(mi32: Mi32, parent=None)[source]

Bases: SimRam

__annotations__ = {}
__init__(mi32: Mi32, parent=None)[source]
Parameters:

  • cellSize – specifies the number of bytes of word (byte is unit of the addres and it does not have to be 8b)

  • clk – clk signal for synchronization

  • parent – parent instance of SimRam (memory will be shared with this instance)

_registerOnClock()[source]
checkRequests()[source]

Check if any request has appeared on interfaces

on_read(addr)[source]
on_req(req)[source]
on_write(addr, val, byteen)[source]

hwtLib.cesnet.mi32.sliding_window module

class hwtLib.cesnet.mi32.sliding_window.Mi32SlidingWindow(hdlName: str | None = None)[source]

Bases: BusBridge

Address space window + offset register which allows to address bigger address space than available on input interface due size of its address signal

Variables:

~.WINDOW_SIZE – size of window to “m” interface also the address of offset register

HDL params:

  • DATA_WIDTH - default value 32 of type int

  • ADDR_WIDTH - default value 32 of type int

  • M_ADDR_WIDTH - default value 33 of type int

  • WINDOW_SIZE - default value 4096 of type int

HDL IO:
schematic
__annotations__ = {}

hwtLib.cesnet.mi32.to_axi4Lite module

class hwtLib.cesnet.mi32.to_axi4Lite.Mi32_to_Axi4Lite(hdlName: str | None = None)[source]

Bases: BusBridge

Bridge from MI32 interface to AxiLite interface

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:
schematic
__annotations__ = {}