hwtLib.cesnet.mi32 package¶

Mi32 is simple bus interfaces commonly used as a service bus. This package contains various components and utilities for this interface.

Submodules¶

hwtLib.cesnet.mi32.axi4Lite_to_mi32 module¶

class hwtLib.cesnet.mi32.axi4Lite_to_mi32.Axi4Lite_to_Mi32(hdl_name_override: Optional[str] = None)[source]¶

Bases: BusBridge

Bridge from AxiLite interface to MI32 interface

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int
RW_PRIORITY - default value READ of type str

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE
m - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER

schematic

hwtLib.cesnet.mi32.buff module¶

class hwtLib.cesnet.mi32.buff.Mi32AddrHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakeSync

Equivalent of Mi32 address/write data channel with HandshakeSync compatible signal names

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
read - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
write - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
be - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
dwr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

class hwtLib.cesnet.mi32.buff.Mi32Buff(hdl_name_override: Optional[str] = None)[source]¶

Bases: BusBridge

Buffer for Mi32 interface

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int
ADDR_BUFF_DEPTH - default value 1 of type int
DATA_BUFF_DEPTH - default value 1 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE
m - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER

HDL components

gen_addr_tmp_reg_0 - of type hwtLib.handshaked.reg.HandshakedReg

schematic

_Mi32_addr_to_Mi32AddrHs(mi32: Mi32, tmp_name)[source]¶

_connect_Mi32AddrHs_to_Mi32(mi32ahs: Mi32AddrHs, mi32: Mi32)[source]¶

hwtLib.cesnet.mi32.builder module¶

class hwtLib.cesnet.mi32.builder.Mi32Builder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]¶

Bases: AxiBuilder

BuffCdcCls = NotImplemented¶

BuffCls¶: alias of _Mi32Buff

classmethod from_axi(parent, axi, name=None)[source]¶: convertor AXI/AxiLite -> Mi32

sliding_window(window_size: int, new_addr_width: int)[source]¶: Instanciate a sliding window with an offset register which allows to virtually extend the addressable memory space

to_axi(axi_cls)[source]¶: convertor Mi32 -> AXI/AXILite

class hwtLib.cesnet.mi32.builder._Mi32Buff(intfCls, hdl_name_override: Optional[str] = None)[source]¶

Bases: Mi32Buff

Mi32Buff constructor which ignores interface in constructor

__init__(intfCls, hdl_name_override: Optional[str] = None)[source]¶

hwtLib.cesnet.mi32.endpoint module¶

class hwtLib.cesnet.mi32.endpoint.Mi32Endpoint(structTemplate, intfCls=<class 'hwtLib.cesnet.mi32.intf.Mi32'>, shouldEnterFn=None)[source]¶

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
bus - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE
decoded - of type hwt.interfaces.structIntf.StructIntf with dtype=struct { <Bits, 32bits, unsigned> field0 <Bits, 32bits, unsigned> field1 } - MASTER

schematic

__init__(structTemplate, intfCls=<class 'hwtLib.cesnet.mi32.intf.Mi32'>, shouldEnterFn=None)[source]¶

Parameters

structTemplate – instance of HStruct which describes address space of this endpoint
intfCls – class of bus interface which should be used
shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()¶

Returns: how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()¶

Returns: size of one word in unit of address

hwtLib.cesnet.mi32.endpoint._example_Mi32Endpoint()[source]¶

hwtLib.cesnet.mi32.interconnectMatrix module¶

class hwtLib.cesnet.mi32.interconnectMatrix.Mi32InterconnectMatrix(hdl_name_override: Optional[str] = None)[source]¶

Bases: BusInterconnect

Simple matrix interconnect for Mi32 interface

HDL params

SLAVES - default value ((0, 256), (256, 256), (<class ‘hwtLib.abstract.busInterconnect.AUTO_ADDR’>, 256), (4096, 4096)) of type tuple
MASTERS - default value ({0, 1, 2, 3},) of type tuple
DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int
MAX_TRANS_OVERLAP - default value 4 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s_0 - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE
m_0 - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER
m_1 - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER
m_2 - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER
m_3 - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER

HDL components

r_data_order - of type hwtLib.handshaked.fifo.HandshakedFifo
s_0_buff - of type hwtLib.cesnet.mi32.buff.Mi32Buff

schematic

hwtLib.cesnet.mi32.interconnectMatrix._example_Mi32InterconnectMatrix()[source]¶

hwtLib.cesnet.mi32.intf module¶

class hwtLib.cesnet.mi32.intf.Mi32(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Interface

Simple memory interface similar to AvalonMM

Variables

~.addr – r/w address
~.rd – read enable
~.wr – write enable
~.ardy – slave address channel ready
~.be – data byte mask for write
~.dwr – write data
~.drd – read data
~.drdy – read data valid

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int

HDL IO

addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
wr - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
ardy - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
be - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
dwr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
drd - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - SLAVE (Master=IN)
drdy - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_getAddrStep()[source]¶

Returns: how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()[source]¶

Returns: size of one word in unit of address

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.cesnet.mi32.intf.Mi32AddrAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

Variables: ~.requests – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)
Note: two valid signals “read”, “write”
Note: one ready_n signal “waitrequest”
Note: on write set data and byteenamble as well

get_data()[source]¶: extract data from interface

classmethod get_ready_signal(intf)[source]¶

get_valid()[source]¶: get “valid” signal

classmethod get_valid_signal(intf)[source]¶

set_data(data)[source]¶: write data to interface

set_valid(val)[source]¶

class hwtLib.cesnet.mi32.intf.Mi32Agent(sim: HdlSimulator, intf: Mi32, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for Mi32 bus interface

Variables

~.requests – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)
~.rData – data read from interface

__init__(sim: HdlSimulator, intf: Mi32, allowNoReset=False)[source]¶

Parameters: rst – tuple (rst signal, rst_negated flag)

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

property r_data¶

r_data_get()[source]¶

r_data_set(v)[source]¶

property requests¶

requests_get()[source]¶

requests_set(v)[source]¶

class hwtLib.cesnet.mi32.intf.Mi32DataAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]¶

Bases: VldSyncedAgent

get_data()[source]¶

classmethod get_valid_signal(intf: Mi32)[source]¶

set_data(data)[source]¶

hwtLib.cesnet.mi32.mi32SimMemSpaceMaster module¶

class hwtLib.cesnet.mi32.mi32SimMemSpaceMaster.Mi32SimMemSpaceMaster(bus, registerMap)[source]¶

Bases: AbstractMemSpaceMaster

Controller of BramPort simulation agent which keeps track of transactions and allows struct like data access

Variables: ~.req – request data, items are tuples (READ, address) or (WRITE, address, data, be_mask)

_read(addr, size, onDone)[source]¶: Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)[source]¶

Add write transaction to agent of interface

Parameters

addr – address value on bus to write on
size – size of data to write in bites
data – data to write on bus
onDone – on write done callback function(sim) -> None

hwtLib.cesnet.mi32.sim_ram module¶

class hwtLib.cesnet.mi32.sim_ram.Mi32SimRam(mi32: Mi32, parent=None)[source]¶

Bases: SimRam

__init__(mi32: Mi32, parent=None)[source]¶

Parameters

cellWidth – width of items in memory
clk – clk signal for synchronization
parent – parent instance of SimRam (memory will be shared with this instance)

_registerOnClock()[source]¶

checkRequests()[source]¶: Check if any request has appeared on interfaces

on_read(addr)[source]¶

on_req(req)[source]¶

on_write(addr, val, byteen)[source]¶

hwtLib.cesnet.mi32.sliding_window module¶

class hwtLib.cesnet.mi32.sliding_window.Mi32SlidingWindow(hdl_name_override: Optional[str] = None)[source]¶

Bases: BusBridge

Address space window + offset register which allows to address bigger address space than available on input interface due size of its address signal

Variables: ~.WINDOW_SIZE – size of window to “m” interface also the address of offset register

HDL params

DATA_WIDTH - default value 32 of type int
ADDR_WIDTH - default value 32 of type int
M_ADDR_WIDTH - default value 33 of type int
WINDOW_SIZE - default value 4096 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
m - of type hwtLib.cesnet.mi32.intf.Mi32 - MASTER
s - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE

schematic

hwtLib.cesnet.mi32.to_axi4Lite module¶

class hwtLib.cesnet.mi32.to_axi4Lite.Mi32_to_Axi4Lite(hdl_name_override: Optional[str] = None)[source]¶

Bases: BusBridge

Bridge from MI32 interface to AxiLite interface

HDL params

ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
m - of type hwtLib.amba.axi4Lite.Axi4Lite - MASTER
s - of type hwtLib.cesnet.mi32.intf.Mi32 - SLAVE

schematic