hwtLib.mem package

A package dedicated to a memory related components, interfaces and utilities.

Subpackages

Submodules

hwtLib.mem.bramPortEndpoint module

class hwtLib.mem.bramPortEndpoint.BramPortEndpoint(structTemplate, hwIOCls=<class 'hwt.hwIOs.std.HwIOBramPort_noClk'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate transaction from BrapmPort interface to interfaces for fields of specified structure.

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • HAS_R - default value True of type bool

  • HAS_W - default value True of type bool

  • HAS_BE - default value False of type bool

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • bus - of type hwt.hwIOs.std.HwIOBramPort_noClk - SLAVE

  • decoded - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 32bits, unsigned> reg0 <HBits, 32bits, unsigned> reg1 <HBits, 32bits, unsigned>[1024] segment0 <HBits, 32bits, unsigned>[1024] segment1 <HBits, 32bits, unsigned>[1028] nonAligned0 } - MASTER

schematic
__annotations__ = {}
__init__(structTemplate, hwIOCls=<class 'hwt.hwIOs.std.HwIOBramPort_noClk'>, shouldEnterFn=None)[source]
Parameters:

  • structTemplate – instance of HStruct which describes address space of this endpoint

  • hwIOCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns:

how many bits is one module of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns:

size of one word in module of address

hwtLib.mem.bramPortEndpoint._example_BramPortEndpoint()[source]

hwtLib.mem.bramPortSimMemSpaceMaster module

class hwtLib.mem.bramPortSimMemSpaceMaster.BramPortSimMemSpaceMaster(bus, registerMap)[source]

Bases: AbstractMemSpaceMaster

Controller of BramPort simulation agent which keeps track of transactions and allows struct like data access

__annotations__ = {}
_read(addr, size, onDone)[source]

Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)[source]

Add write transaction to agent of interface

Parameters:

  • addr – address value on bus to write on

  • size – size of data to write in bites

  • data – data to write on bus

  • onDone – on write done callback function(sim) -> None

hwtLib.mem.cam module

class hwtLib.mem.cam.Cam(hdlName: str | None = None)[source]

Bases: HwModule

Content addressable memory. MATCH_LATENCY = 1

HDL params:

  • KEY_WIDTH - default value 15 of type int

  • ITEMS - default value 32 of type int

  • USE_VLD_BIT - default value True of type boolif true the validity bit is a part of the CAM record

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • match - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

  • out - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

  • write - of type hwtLib.commonHwIO.addr_data.HwIOAddrDataVldRdVld - SLAVE

schematic
__annotations__ = {}
_declr_match_io()[source]
matchHandler(mem, key: HwIODataRdVld, match_res: HwIODataRdVld)[source]
writeHandler(mem)[source]
class hwtLib.mem.cam.CamMultiPort(hdlName: str | None = None)[source]

Bases: Cam

A variant of Cam with multiple ports for lookup

HDL params:

  • KEY_WIDTH - default value 15 of type int

  • ITEMS - default value 32 of type int

  • USE_VLD_BIT - default value True of type bool

  • MATCH_PORT_CNT - default value 2 of type intnumber of CAM ports for matching, if None there is only as single port otherwise there is an array of such a ports of specified size

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • match - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • out - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

  • write - of type hwtLib.commonHwIO.addr_data.HwIOAddrDataVldRdVld - SLAVE

schematic
__annotations__ = {}
_declr_match_io()[source]
matchHandler(mem, key: HwIODataRdVld, match_res: HwIODataRdVld)[source]
hwtLib.mem.cam._example_CamMultiPort()[source]

hwtLib.mem.cuckooHashTablWithRam module

class hwtLib.mem.cuckooHashTablWithRam.CuckooHashTableWithRam(polynomials)[source]

Bases: CuckooHashTable

A cuckoo hash table core with integrated memory

HDL params:

  • TABLE_SIZE - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • KEY_WIDTH - default value 8 of type int

  • LOOKUP_KEY - default value False of type bool

  • TABLE_CNT - default value 2 of type int

  • MAX_LOOKUP_OVERLAP - default value 16 of type int

  • MAX_REINSERT - default value 15 of type int

  • POLYNOMIALS - default value (<class ‘hwtLib.logic.crcPoly.CRC_32’>, <class ‘hwtLib.logic.crcPoly.CRC_32C’>) of type tuple

HDL IO:
HDL components:
schematic
__annotations__ = {}
__init__(polynomials)[source]
hwtLib.mem.cuckooHashTablWithRam._example_CuckooHashTableWithRam()[source]

hwtLib.mem.cuckooHashTable module

class hwtLib.mem.cuckooHashTable.CuckooHashTable[source]

Bases: HashTableCore

Cuckoo hash uses more tables with different hash functions

Lookup is performed in all tables at once and if item is found in any table. The item is found. Otherwise item is not in tables. lookup time: O(1)

Insert has to first lookup if item is in any table. If any table contains invalid item. The item is stored there and insert operation is complete. If there was a valid item under this key in all tables. One is selected and it is swapped with current item. Insert process then repeats with this item. Until some invalid item (empty slot) is found.

Inserting into table does not have to be successful and in this case, fsm ends up in infinite loop and it will be reinserting items for ever. insert time: O(inf)

_images/CuckooHashTable.png
HDL params:

  • TABLE_SIZE - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • KEY_WIDTH - default value 8 of type int

  • LOOKUP_KEY - default value False of type bool

  • TABLE_CNT - default value 2 of type int

  • MAX_LOOKUP_OVERLAP - default value 16 of type int

  • MAX_REINSERT - default value 15 of type int

HDL IO:
schematic
__annotations__ = {}
__init__()[source]
_declr_outer_io()[source]
clean_addr_iterator(en)[source]
configure_tables(tables: List[HashTableCore])[source]

share the configuration with the table engines

insertRes_driver(state, stash, insertAck, insertFinal, isDelete)[source]
insert_addr_select(insertTargetOH, state, cleanAddr)[source]

Select a insert address

lookupRes_driver(state: RtlSignal, lookupFoundOH: RtlSignal)[source]

If lookup request comes from external interface “lookup” propagate results from tables to “lookupRes”.

lookup_trans_cntr()[source]

create a counter of pure lookup operations in progress

stash_load(isIdle, lookupResNext, insertTargetOH, stash, lookup_not_in_progress, another_lookup_possible)[source]

load a stash register from lookup/insert/delete interface

tables_insert_driver(state: RtlSignal, insertTargetOH: RtlSignal, insertIndex: RtlSignal, stash: RtlSignal)[source]
Parameters:

  • state – state register of main FSM

  • insertTargetOH – index of table where insert should be performed, one hot encoding

  • insertIndex – address for table where item should be placed

  • stash – stash register with data for insert/lookup/delete from table

tables_lookupRes_resolver(insertResRead: RtlSignal)[source]

Control lookupRes interface for each table

tables_lookup_driver(state: RtlSignal, tableKey: RtlSignal, lookup_en: RtlSignal)[source]

Connect a lookup ports of all tables

hwtLib.mem.cuckooHashTable_intf module

class hwtLib.mem.cuckooHashTable_intf.HwIOCuckooInsert(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

Cuckoo hash insert interface

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.cuckooHashTable_intf.HwIOCuckooInsertAgent(sim, hwIO)[source]

Bases: HwIODataRdVldAgent

Agent for HwIOCuckooInsert interface

__annotations__ = {}
__init__(sim, hwIO)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.cuckooHashTable_intf.HwIOCuckooInsertRes(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIOCuckooInsert

An interface with an result of insert operation.

Variables:

pop – signal if 1 the key and data on this interface contains the item which had to be removed during insert because the insertion limit was exceeded

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.cuckooHashTable_intf.HwIOCuckooInsertResAgent(sim, hwIO)[source]

Bases: HwIOCuckooInsertAgent

Agent for HwIOCuckooInsertRes interface

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.fifo module

class hwtLib.mem.fifo.Fifo(hdlName: str | None = None)[source]

Bases: HwModule

Generic FIFO usually mapped to BRAM. :note: 1clk to write, 1clk to read

Variables:

  • ~.EXPORT_SIZE – parameter, if true “size” signal will be exported

  • ~.size – optional signal with count of items stored in this fifo

  • ~.EXPORT_SPACE – parameter, if true “space” signal is exported

  • ~.space – optional signal with count of items which can be added to this fifo

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value True of type bool

  • EXPORT_SPACE - default value True of type bool

  • INIT_DATA - default value (1, 2, 3) of type tuple

  • INIT_DATA_FIRST_WORD - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.std.HwIOFifoWriter - SLAVE

  • dataOut - of type hwt.hwIOs.std.HwIOFifoReader - MASTER

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits, unsigned> - MASTER

  • space - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits, unsigned> - MASTER

schematic
__annotations__ = {}
_declr_size_and_space()[source]
constructFifoSizeLogic(fifo_read: HBitsRtlSignal, fifo_write: HBitsRtlSignal)[source]
constructFifoSpaceLogic(fifo_read: HBitsRtlSignal, fifo_write: HBitsRtlSignal)[source]
hwtLib.mem.fifo._example_Fifo()[source]

hwtLib.mem.fifoArray module

class hwtLib.mem.fifoArray.FifoArray(hdlName: str | None = None)[source]

Bases: HwModule

This component is an array of list nodes, which can be used to emulate multiple FIFOs. The memory is shared and the number of lists stored in this array is limited only by memory.

Corresponds to data structure:

// note that in implementation each part of struct item is stored in separate array
struct item {
  value_t value;
  item * next;
  bool valid;
  bool last;
};

item items[ITEMS];
HDL params:

  • ITEMS - default value 4 of type int

  • DATA_WIDTH - default value 8 of type int

HDL IO:
schematic
__annotations__ = {}
class hwtLib.mem.fifoArray.FifoArrayInsertInterface(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSyncBiDirectionalData

Variables:

  • ~.append – if append = 1 the item is appended to last list item specified using “addr” else new list is created and “addr” value is ignored

  • ~.addr – an address with potential end of the list

  • ~.data – data to store in next list node

  • ~.addr_ret – an address where the item was inserted to

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • append - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • addr_ret - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoArray.FifoArrayInsertInterfaceAgent(sim, hwIO)[source]

Bases: HwIORdVldSyncBiDirectionalDataAgent

Simulation agent for FifoArrayInsertInterface interface

__annotations__ = {}
get_data()[source]

extract data from interface

onDriverWriteAck()[source]

read din

onMonitorReady()[source]

write din

set_data(data)[source]

write data to interface

class hwtLib.mem.fifoArray.FifoArrayPopInterface(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIOAddrInDataOutRdVld

Variables:

  • ~.addr – the address of the list head to read from:

  • ~.data – the return data which was read

  • ~.last – flag which tell if this node was last in this list and thus this list is now empty and deallocated

  • ~.addr_next – address on a next item in this FIFO

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • addr_next - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoArray.FifoArrayPopInterfaceAgent(sim, hwIO)[source]

Bases: HwIOAddrInDataOutRdVldAgent

Simulation agent for FifoArrayPopInterfaceAgent interface

__annotations__ = {}
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.fifoAsync module

class hwtLib.mem.fifoAsync.FifoAsync(hdlName: str | None = None)[source]

Bases: Fifo

Asynchronous FIFO using BRAM/LUT memory, based on: * https://github.com/ZipCPU/website/blob/master/examples/afifo.v * https://github.com/alexforencich/verilog-axis/blob/master/rtl/axis_async_fifo.v

HDL params:

  • DATA_WIDTH - default value 64 of type int

  • DEPTH - default value 4 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.constants.NOT_SPECIFIED’> of type type

  • IN_FREQ - default value 100000000 of type int

  • OUT_FREQ - default value 100000000 of type int

HDL IO:

  • dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.std.HwIOFifoWriter - SLAVE

  • dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataOut - of type hwt.hwIOs.std.HwIOFifoReader - MASTER

schematic
__annotations__ = {}
_addr_reg_and_cdc(reg_name, clk_in, clk_out)[source]

Create a register for head/tail FIFO reader/writter position with gray encoded value propagated to other clock domain

hwtLib.mem.fifoAsync._example_FifoAsync()[source]

hwtLib.mem.fifoCopy module

class hwtLib.mem.fifoCopy.FifoCopy(hdlName: str | None = None)[source]

Bases: Fifo

Fifo with an extra signals to control replay of lastly stored data

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.constants.NOT_SPECIFIED’> of type type

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.std.HwIOFifoWriter - SLAVE

  • dataOut - of type hwt.hwIOs.std.HwIOFifoReader - MASTER

  • dataOut_copy_frame - of type hwt.hwIOs.std.HwIODataVld - SLAVE The channel which drives when to capture start of the frame and when to start relaying previously stored frame from the marked start

schematic
__annotations__ = {}
hwtLib.mem.fifoCopy._example_FifoCopy()[source]

hwtLib.mem.fifoDrop module

class hwtLib.mem.fifoDrop.FifoDrop(hdlName: str | None = None)[source]

Bases: Fifo

Fifo with an extra signals for writter which allows to commit or discard data chung writen in to fifo.

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value True of type bool

  • EXPORT_SPACE - default value True of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.constants.NOT_SPECIFIED’> of type type

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.mem.fifoDrop.FifoWriterDropable - SLAVE

  • dataOut - of type hwt.hwIOs.std.HwIOFifoReader - MASTER

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits, unsigned> - MASTER

  • space - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits, unsigned> - MASTER

schematic
__annotations__ = {}
class hwtLib.mem.fifoDrop.FifoWriterDropable(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIOFifoWriter

FIFO write port interface witch commit and discard signal used to drop data chunks already written in FIFO

Variables:

  • ~.commit – if 1 all the written data are made available to reader, including current data word

  • ~.discard – if 1 all written data which were not commited are discarded including current data word

HDL params:

  • DATA_WIDTH - default value 8 of type int

HDL IO:

  • en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • wait - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • commit - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • discard - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_getIpCoreIntfClass()[source]
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoDrop.FifoWriterDropableAgent(sim: HdlSimulator, hwIO: HwIOFifoWriter, allowNoReset=False)[source]

Bases: HwIOFifoWriterAgent

__annotations__ = {}
get_data()[source]
set_data(d)[source]
hwtLib.mem.fifoDrop._example_FifoDrop()[source]

hwtLib.mem.fifoPtrLogic module

class hwtLib.mem.fifoPtrLogic.FifoPtrLogic(parent: HwModule, DEPTH: int, RAM_SIZE: int | None = None, INIT_SIZE: int = 0)[source]

Bases: object

Note:

r_ptr=index which is going to be read

Note:

w_ptr=index which is going to be written

Variant of read_ptr/write_ptr implementations

note:

in all variants r_ptr is initialized to 0, w_ptr to number of interms preloaded in FIFO

note:

variants with ram.R_LATENCY=1 will latch mem[rd_ptr] if fifo_read so the mem[rd_ptr] is not safe to be written in any variant unless the fifo is empty

Variant with r_wait = w_ptr == r_ptr

  • EFFECTIVE_DEPTH = DEPTH - 1

  • timing issues: w_wait expressions contain add and saturation

Variant with r_wait = count != 0

Variant with item lock flag

Uses explicit flag to check if the w_ptr moved to r_ptr or r_ptr moved to w_ptr * EFFECTIVE_DEPTH = DEPTH

Variant with XORed item lock flag

Distributed last_was_r set to crossed0_r, crossed0_w crossed0_r/crossed0_w is filipped if pointer overflows * EFFECTIVE_DEPTH = DEPTH .. code-block::python

r_is_before_w = crossed0_r == crossed0_w w_is_before_r = crossed0_r != crossed0_w full = w_wait = (w_ptr._eq(r_ptr)) & ~r_is_before_w empty = r_wait = (w_ptr._eq(r_ptr)) & r_is_before_w

__init__(parent: HwModule, DEPTH: int, RAM_SIZE: int | None = None, INIT_SIZE: int = 0)[source]
_fifo_ptr_distance(ptr0: HBitsRtlSignal, ptr1: HBitsRtlSignal)[source]

Computes distance from ptr0 to ptr1

_is_fifo_ptr_add_possible(ptr0: RtlSignal, ptr1: RtlSignal | int, allow_eq: RtlSignal, ptr0IncrVal: HBitsRtlSignal | int) → RtlSignal[source]
static _normalize_EnWaitIncrValTuple(en_wait_incrVal: tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal]) → tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal][source]
_should_use_distributed_locks(write_en_wait_incrVal: tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal], read_en_wait_incrVal_list: list[tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal]]) → bool[source]

Use distibuted locks if the check for overflow needs to check incrVal because

_uadd_with_modulo(v: RtlSignal, incrVal: int | RtlSignal)[source]
_usub_with_modulo(v: RtlSignal, decrVal: int | RtlSignal)[source]
fifo_pointers(write_en_wait_incrVal: tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal], read_en_wait_incrVal_list: list[tuple[HBitsRtlSignal, HBitsRtlSignal] | tuple[HBitsRtlSignal, HBitsRtlSignal, int | HBitsRtlSignal]]) → list[tuple[RtlSignal, RtlSignal]][source]

Create fifo writer and reader pointers and enable/wait logic This functions supports multiple reader pointers

Note:

Multiple read pointers are useful when the data in fifo passes

through multiple states, this efficiently means that instead of two FIFOs betwen some components we can use just 1 with multiple read poiners. For example 1st read pointer may represent if the data is beeing processed (lock) and the second if the data processing was finished and the item in fifo is deallocated (commit).

Note:

*_en are inputs, *_wait, are outputs

Note:

en=1 and wait=1 will result in nop and will not cause underflow/overflow

Attention:

writer pointer next logic check only last reader pointer

Returns:

list, tule(en, ptr) for writer and each reader

hwtLib.mem.hashTableCore module

class hwtLib.mem.hashTableCore.HashTableCore(polynome)[source]

Bases: HwModule

Generic hash table, in block RAM there is a input key which is hashed ad this has is used as an index into memory item on this place is checked and returned on “lookupRes” interface (item does have to be found, see “found” flag in LookupResultIntf)

memory is an array of items in format

struct item {
    bool item_vld;
    data_t data;
    key_t key;
};
Variables:

  • ~.ITEMS_CNT – number of items in memory of hash table

  • ~.KEY_WIDTH – width of the key used by hash table

  • ~.DATA_WIDTH – width of data, can be zero and then no data interface is instantiated

  • ~.LOOKUP_ID_WIDTH – width of id signal for lookup (tag used only by parent component to mark this lookup for later result processing, can be 0)

  • ~.LOOKUP_HASH – flag if lookup interface should have hash signal

  • ~.LOOKUP_KEY – flag if lookup interface should have key signal

  • ~.POLYNOME – polynome for crc hash used in this table

_images/HashTableCore.png
HDL params:

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO:
HDL components:
schematic
__annotations__ = {}
__init__(polynome)[source]
_declr_common()[source]
insertLogic(ramW: HwIOAddrDataRdVld)[source]
lookupLogic(ramR: HwIORamRdVldR)[source]
parseItem(sig)[source]

Parse data stored in hash table

hwtLib.mem.hashTableCore._example_HashTableCore()[source]

hwtLib.mem.hashTableCoreWithRam module

class hwtLib.mem.hashTableCoreWithRam.HashTableCoreWithRam(polynome)[source]

Bases: HashTableCore

HDL params:

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • io - of type hwtLib.mem.hashTable_intf.HwIOHashTable - SLAVE

HDL components:
schematic
__annotations__ = {}
hwtLib.mem.hashTableCoreWithRam._example_HashTableCoreWithRam()[source]

hwtLib.mem.hashTable_intf module

class hwtLib.mem.hashTable_intf.HwIOHashTable(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO:
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.HwIOHashTableAgent(sim: HdlSimulator, hwIO: HwIOHashTable)[source]

Bases: AgentBase

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: HwIOHashTable)[source]
getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

class hwtLib.mem.hashTable_intf.HwIOInsert(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

HDL params:

  • HASH_WIDTH - default value 8 of type int

  • KEY_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 0 of type int

HDL IO:

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • hash - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • key - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

  • item_vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.HwIOInsertAgent(sim: HdlSimulator, hwIO: HwIOInsert)[source]

Bases: HwIODataRdVldAgent

Simulation agent for .HwIOInsert interface

data format:

  • if interface has data signal, data format is tuple (hash, key, data, item_vld)

  • if interface does not have data signal, data format is tuple (hash, key, item_vld)

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: HwIOInsert)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.hashTable_intf.HwIOLookupKey(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

HDL params:

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • KEY_WIDTH - default value 8 of type int

HDL IO:

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • key - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.HwIOLookupKeyAgent(sim: HdlSimulator, hwIO: HwIOLookupKey)[source]

Bases: HwIODataRdVldAgent

Simulation agent for HwIOLookupKey interface

__annotations__ = {}
__init__(sim: HdlSimulator, hwIO: HwIOLookupKey)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.hashTable_intf.HwIOLookupResult(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIODataRdVld

HwIO for result of lookup in hash table

Variables:

  • ~.HASH_WIDTH – width of the hash used by hash table

  • ~.KEY_WIDTH – width of the key used by hash table

  • ~.LOOKUP_HASH – flag if this interface should have hash signal

  • ~.LOOKUP_KEY – flag if this interface should have hash signal

  • ~.hash – hash for this key (= index in this table)

  • ~.key – original key which was searched for

  • ~.data – data under this key

  • ~.occupied – flag which tells if there is an valid item under this key

HDL params:

  • HASH_WIDTH - default value 8 of type int

  • KEY_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 0 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO:

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • found - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • occupied - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.HwIOLookupResultAgent(sim, hwIO)[source]

Bases: HwIODataRdVldAgent

Simulation agent for .HwIOLookupResult data is stored in .data data format is tuple (hash, key, data, found) but some items can be missing depending on configuration of interface

__annotations__ = {}
__init__(sim, hwIO)[source]
Parameters:

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.lutRam module

class hwtLib.mem.lutRam.RAM64X1S(hdlName: str | None = None)

Bases: HwModule

__annotations__ = {}
hwtLib.mem.lutRam.mkLutRamCls(DATA_WIDTH)[source]

Lut ram generator, hdl code will be excluded from serialization because we expect vendor library to contains it

hwtLib.mem.ram module

class hwtLib.mem.ram.RamMultiClock(hdlName: str | None = None)[source]

Bases: HwModule

RAM where each port has an independent clock. It can be configured to true dual port RAM etc. It can also be configured to have write mask or to be composed from multiple smaller memories.

HDL params:

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value 2 of type int

  • HAS_BE - default value False of type bool

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

  • READ_LATENCY - default value 1 of type int

HDL IO:

  • port - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

schematic
PORT_CLS

alias of HwIOBramPort

__annotations__ = {}
class hwtLib.mem.ram.RamSingleClock(hdlName: str | None = None)[source]

Bases: HwModule

RAM/ROM with only one clock signal. It can be configured to have arbitrary number of ports. It can also be configured to have write mask or to be composed from multiple smaller memories.

HDL params:

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value 1 of type intHwParam which specifies number of ram ports, it can be int or tuple of READ_WRITE, WRITE, READ to specify rw access for each port separately

  • HAS_BE - default value False of type boolHwParam, if True the write ports will have byte enable signal

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

  • READ_LATENCY - default value 1 of type intlatency in clock cycles from read enable=1 to read data appear on the output 0=distmem, 1=BRAM

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • port - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

schematic
PORT_CLS

alias of HwIOBramPort_noClk

__annotations__ = {}
_declr_children()[source]
_declr_ports()[source]
static connect_HwIOBramPort_noClk_to_mem(clk: RtlSignal, read_latency, port: HwIOBramPort_noClk, mem: RtlSignal)[source]
delegate_to_children()[source]
static mem_write(mem, port: HwIOBramPort_noClk)[source]

hwtLib.mem.ramCumulativeMask module

class hwtLib.mem.ramCumulativeMask.BramPort_withReadMask_withoutClk(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIOBramPort_noClk

Block RAM port with a en handshaked interface for arbitration

Variables:

  • do_accumulate – HwIOSignal if 1 the mask bits are or-ed together with the value in stored in ram

  • do_overwrite – HwIOSignal if 1 the the data mask in ram is set to current we value

  • dout_mask – Read port contains this signal which contains the cumulative validity mask for the data.

HDL params:

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • HAS_R - default value True of type bool

  • HAS_W - default value True of type bool

  • HAS_BE - default value False of type bool

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN

  • dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN (Master=IN)

  • en - of type hwt.hwIOs.std.HwIORdVldSync - UNKNOWN

  • we - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
class hwtLib.mem.ramCumulativeMask.RamCumulativeMask(hdlName: str | None = None)[source]

Bases: RamSingleClock

RAM which stores also byte enable value for each data word (to keep track of which bytes were updated).

Note:

BramPort_withReadMask_withoutClk contains the informations about how to control this component.

PORT_CLS

alias of BramPort_withReadMask_withoutClk

__annotations__ = {}
hwtLib.mem.ramCumulativeMask.is_mask_byte_unaligned(mask_signal: RtlSignal) → RtlSignal[source]

hwtLib.mem.ramTransactional module

class hwtLib.mem.ramTransactional.RamTransactional(hdlName: str | None = None)[source]

Bases: HwModule

A RAM with 1 read port and 1 write port with flush before functionality. If the flush is activate the current data is read first before it is overwritten by write data. This memory supports multiword transaction and the swap, read and write is atomic in relation with other transactions.

_images/RamTransactional.png
HDL params:

  • ADDR_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 8 of type int

  • WORD_WIDTH - default value 16 of type int

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • W_PRIV_T - default value None of type None

  • R_ID_WIDTH - default value 0 of type int

HDL IO:
HDL components:
schematic
__annotations__ = {}
_declr_io()[source]
construct_r_meta(flush_req: RtlSignal, read_pending: RtlSignal, r: HwIORamRdVldR, w: HwIOAddrDataRdVld, w_index: HwIOStruct, r_index_o: HwIOStruct) → HandshakedReg[source]
construct_ram_io() → Tuple[HwIORamRdVldR, HwIOAddrDataRdVld][source]
construct_read_part(r: TransRamHsR, w_addr: RtlSignal, da_r: HwIORamRdVldR, r_meta: List[HandshakedReg], flush_req: RtlSignal, read_pending: RtlSignal, r_index_o: HwIOStruct, r_index_i: HwIOStruct, flush_data: TransRamHsW)[source]
construct_write_part(w: TransRamHsW, da_r: HwIORamRdVldR, da_w: HwIOAddrDataRdVld, w_index_i: HwIOStruct, w_index_o, r_index_o, r_meta_din: HwIOStructRdVld)[source]

hwtLib.mem.ramTransactional_io module

class hwtLib.mem.ramTransactional_io.TransRamHsR(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

Handshaked RAM port

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

  • ID_WIDTH - default value 0 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO:
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsR_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

HDL params:

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsW(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIO

HDL params:

  • DATA_WIDTH - default value 64 of type int

  • USE_STRB - default value True of type bool

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

  • USE_FLUSH - default value True of type bool

HDL IO:
__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsW_addr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: TransRamHsR_addr

HDL params:

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

  • USE_FLUSH - default value True of type bool

HDL IO:

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

  • vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

  • rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

  • flush - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}
_initSimAgent(sim: HdlSimulator)[source]

hwtLib.mem.ramXor module

class hwtLib.mem.ramXor.RamXorSingleClock(hdlName: str | None = None)[source]

Bases: RamSingleClock

Multiport XOR based RAM with only one clock signal

HDL params:

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value (‘WRITE’, ‘WRITE’, ‘READ’) of type tuple

  • HAS_BE - default value False of type bool

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

  • READ_LATENCY - default value 1 of type int

  • PRIMITIVE_MEMORY_PORTS - default value (‘WRITE’, ‘READ’) of type tuplememory port of native memory from which this memory is built.

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst - of type hwt.hwIOs.std.HwIORst with dtype=<HBits, 1bit> - SLAVE

  • port - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

HDL components:
schematic
__annotations__ = {}