hwtLib.mem package

A package dedicated to a memory related components, interfaces and utilities.

Submodules

hwtLib.mem.bramPortEndpoint module

class hwtLib.mem.bramPortEndpoint.BramPortEndpoint(structTemplate, intfCls=<class 'hwt.interfaces.std.BramPort_withoutClk'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate transaction from BrapmPort interface to interfaces for fields of specified structure.

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • HAS_R - default value True of type bool

  • HAS_W - default value True of type bool

  • HAS_BE - default value False of type bool

HDL IO
schematic
__init__(structTemplate, intfCls=<class 'hwt.interfaces.std.BramPort_withoutClk'>, shouldEnterFn=None)[source]
Parameters

  • structTemplate – instance of HStruct which describes address space of this endpoint

  • intfCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns

size of one word in unit of address

hwtLib.mem.bramPortEndpoint._example_BramPortEndpoint()[source]

hwtLib.mem.bramPortSimMemSpaceMaster module

class hwtLib.mem.bramPortSimMemSpaceMaster.BramPortSimMemSpaceMaster(bus, registerMap)[source]

Bases: AbstractMemSpaceMaster

Controller of BramPort simulation agent which keeps track of transactions and allows struct like data access

_read(addr, size, onDone)[source]

Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)[source]

Add write transaction to agent of interface

Parameters

  • addr – address value on bus to write on

  • size – size of data to write in bites

  • data – data to write on bus

  • onDone – on write done callback function(sim) -> None

hwtLib.mem.cam module

class hwtLib.mem.cam.Cam(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

Content addressable memory. MATCH_LATENCY = 1

HDL params

  • KEY_WIDTH - default value 15 of type int

  • ITEMS - default value 32 of type int

  • USE_VLD_BIT - default value True of type boolif true the validity bit is a part of the CAM record

HDL IO
schematic
_declr_match_io()[source]
matchHandler(mem, key: Handshaked, match_res: Handshaked)[source]
writeHandler(mem)[source]
class hwtLib.mem.cam.CamMultiPort(hdl_name_override: Optional[str] = None)[source]

Bases: Cam

A variant of Cam with multiple ports for lookup

HDL params

  • KEY_WIDTH - default value 15 of type int

  • ITEMS - default value 32 of type int

  • USE_VLD_BIT - default value True of type bool

  • MATCH_PORT_CNT - default value 2 of type intnumber of CAM ports for matching, if None there is only as single port otherwise there is an array of such a ports of specified size

HDL IO
schematic
_declr_match_io()[source]
matchHandler(mem, key: Handshaked, match_res: Handshaked)[source]
hwtLib.mem.cam._example_CamMultiPort()[source]

hwtLib.mem.cuckooHashTablWithRam module

class hwtLib.mem.cuckooHashTablWithRam.CuckooHashTableWithRam(polynomials)[source]

Bases: CuckooHashTable

A cuckoo hash table core with integrated memory

HDL params

  • TABLE_SIZE - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • KEY_WIDTH - default value 8 of type int

  • LOOKUP_KEY - default value False of type bool

  • TABLE_CNT - default value 2 of type int

  • MAX_LOOKUP_OVERLAP - default value 16 of type int

  • MAX_REINSERT - default value 15 of type int

  • POLYNOMIALS - default value (<class ‘hwtLib.logic.crcPoly.CRC_32’>, <class ‘hwtLib.logic.crcPoly.CRC_32C’>) of type tuple

HDL IO
HDL components
schematic
__init__(polynomials)[source]
hwtLib.mem.cuckooHashTablWithRam._example_CuckooHashTableWithRam()[source]

hwtLib.mem.cuckooHashTable module

class hwtLib.mem.cuckooHashTable.CuckooHashTable[source]

Bases: HashTableCore

Cuckoo hash uses more tables with different hash functions

Lookup is performed in all tables at once and if item is found in any table. The item is found. Otherwise item is not in tables. lookup time: O(1)

Insert has to first lookup if item is in any table. If any table contains invalid item. The item is stored there and insert operation is complete. If there was a valid item under this key in all tables. One is selected and it is swapped with current item. Insert process then repeats with this item. Until some invalid item (empty slot) is found.

Inserting into table does not have to be successful and in this case, fsm ends up in infinite loop and it will be reinserting items for ever. insert time: O(inf)

_images/CuckooHashTable.png
HDL params

  • TABLE_SIZE - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • KEY_WIDTH - default value 8 of type int

  • LOOKUP_KEY - default value False of type bool

  • TABLE_CNT - default value 2 of type int

  • MAX_LOOKUP_OVERLAP - default value 16 of type int

  • MAX_REINSERT - default value 15 of type int

HDL IO
schematic
__init__()[source]
_declr_outer_io()[source]
clean_addr_iterator(en)[source]
configure_tables(tables: List[HashTableCore])[source]

share the configuration with the table engines

insertRes_driver(state, stash, insertAck, insertFinal, isDelete)[source]
insert_addr_select(insertTargetOH, state, cleanAddr)[source]

Select a insert address

lookupRes_driver(state: RtlSignal, lookupFoundOH: RtlSignal)[source]

If lookup request comes from external interface “lookup” propagate results from tables to “lookupRes”.

lookup_trans_cntr()[source]

create a counter of pure lookup operations in progress

stash_load(isIdle, lookupResNext, insertTargetOH, stash, lookup_not_in_progress, another_lookup_possible)[source]

load a stash register from lookup/insert/delete interface

tables_insert_driver(state: RtlSignal, insertTargetOH: RtlSignal, insertIndex: RtlSignal, stash: RtlSignal)[source]
Parameters

  • state – state register of main FSM

  • insertTargetOH – index of table where insert should be performed, one hot encoding

  • insertIndex – address for table where item should be placed

  • stash – stash register with data for insert/lookup/delete from table

tables_lookupRes_resolver(insertResRead: RtlSignal)[source]

Control lookupRes interface for each table

tables_lookup_driver(state: RtlSignal, tableKey: RtlSignal, lookup_en: RtlSignal)[source]

Connect a lookup ports of all tables

hwtLib.mem.cuckooHashTable_intf module

class hwtLib.mem.cuckooHashTable_intf.CInsertIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakeSync

Cuckoo hash insert interface

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.cuckooHashTable_intf.CInsertIntfAgent(sim, intf)[source]

Bases: HandshakedAgent

Agent for CInsertIntf interface

__init__(sim, intf)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.cuckooHashTable_intf.CInsertResIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: CInsertIntf

An interface with an result of insert operation.

Variables

pop – signal if 1 the key and data on this interface contains the item which had to be removed during insert because the insertion limit was exceeded

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.cuckooHashTable_intf.CInsertResIntfAgent(sim, intf)[source]

Bases: CInsertIntfAgent

Agent for CInsertResIntf interface

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.fifo module

class hwtLib.mem.fifo.Fifo(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

Generic FIFO usually mapped to BRAM.

Variables

  • ~.EXPORT_SIZE – parameter, if true “size” signal will be exported

  • ~.size – optional signal with count of items stored in this fifo

  • ~.EXPORT_SPACE – parameter, if true “space” signal is exported

  • ~.space – optional signal with count of items which can be added to this fifo

HDL params

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value True of type bool

  • EXPORT_SPACE - default value True of type bool

  • INIT_DATA - default value (1, 2, 3) of type tuple

  • INIT_DATA_FIRST_WORD - default value 0 of type int

HDL IO
schematic
_declr_size_and_space()[source]
fifo_pointers(DEPTH: int, write_en_wait: Tuple[RtlSignal, RtlSignal], read_en_wait_list: List[Tuple[RtlSignal, RtlSignal]]) → List[Tuple[RtlSignal, RtlSignal]][source]

Create fifo writer and reader pointers and enable/wait logic This functions supports multiple reader pointers

Attention

writer pointer next logic check only last reader pointer

Returns

list, tule(en, ptr) for writer and each reader

hwtLib.mem.fifo._example_Fifo()[source]

hwtLib.mem.fifoArray module

class hwtLib.mem.fifoArray.FifoArray(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

This component is an array of list nodes, which can be used to emulate multiple FIFOs. The memory is shared and the number of lists stored in this array is limited only by memory.

Corresponds to data structure:

// note that in implementation each part of struct item is stored in separate array
struct item {
  value_t value;
  item * next;
  bool valid;
  bool last;
};

item items[ITEMS];
HDL params

  • ITEMS - default value 4 of type int

  • DATA_WIDTH - default value 8 of type int

HDL IO
schematic
class hwtLib.mem.fifoArray.FifoArrayInsertInterface(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakedBiDirectional

Variables

  • ~.append – if append = 1 the item is appended to last list item specified using “addr” else new list is created and “addr” value is ignored

  • ~.addr – an address with potential end of the list

  • ~.data – data to store in next list node

  • ~.addr_ret – an address where the item was inserted to

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoArray.FifoArrayInsertInterfaceAgent(sim, intf)[source]

Bases: HandshakedBiDirectionalAgent

Simulation agent for FifoArrayInsertInterface interface

get_data()[source]

extract data from interface

onDriverWriteAck()[source]

read din

onMonitorReady()[source]

write din

set_data(data)[source]

write data to interface

class hwtLib.mem.fifoArray.FifoArrayPopInterface(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: AddrInDataOutHs

Variables

  • ~.addr – the address of the list head to read from:

  • ~.data – the return data which was read

  • ~.last – flag which tell if this node was last in this list and thus this list is now empty and deallocated

  • ~.addr_next – address on a next item in this FIFO

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoArray.FifoArrayPopInterfaceAgent(sim, intf)[source]

Bases: AddrInDataOutHsAgent

Simulation agent for FifoArrayPopInterfaceAgent interface

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.fifoAsync module

class hwtLib.mem.fifoAsync.FifoAsync(hdl_name_override: Optional[str] = None)[source]

Bases: Fifo

Asynchronous fifo using BRAM/LUT memory, based on: * https://github.com/ZipCPU/website/blob/master/examples/afifo.v * https://github.com/alexforencich/verilog-axis/blob/master/rtl/axis_async_fifo.v

HDL params

  • DATA_WIDTH - default value 64 of type int

  • DEPTH - default value 4 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED’> of type type

  • IN_FREQ - default value 100000000 of type int

  • OUT_FREQ - default value 100000000 of type int

HDL IO
schematic
_addr_reg_and_cdc(reg_name, clk_in, clk_out)[source]

Create a register for head/tail FIFO reader/writter position with gray encoded value propagated to other clock domain

hwtLib.mem.fifoAsync._example_FifoAsync()[source]

hwtLib.mem.fifoCopy module

class hwtLib.mem.fifoCopy.FifoCopy(hdl_name_override: Optional[str] = None)[source]

Bases: Fifo

Fifo with an extra signals to control replay of lastly stored data

HDL params

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED’> of type type

HDL IO
schematic
hwtLib.mem.fifoCopy._example_FifoCopy()[source]

hwtLib.mem.fifoDrop module

class hwtLib.mem.fifoDrop.FifoDrop(hdl_name_override: Optional[str] = None)[source]

Bases: Fifo

Fifo with an extra signals for writter which allows to commit or discard data chung writen in to fifo.

HDL params

  • DATA_WIDTH - default value 8 of type int

  • DEPTH - default value 16 of type int

  • EXPORT_SIZE - default value True of type bool

  • EXPORT_SPACE - default value True of type bool

  • INIT_DATA - default value () of type tuple

  • INIT_DATA_FIRST_WORD - default value <class ‘hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED’> of type type

HDL IO
schematic
class hwtLib.mem.fifoDrop.FifoWriterDropable(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: FifoWriter

FIFO write port interface witch commit and discard signal used to drop data chunks already written in fifo

Variables

  • ~.commit – if 1 all the written data are made available to reader, including current data word

  • ~.discard – if 1 all written data which were not commited are discarded includeing current data word

HDL params

  • DATA_WIDTH - default value 8 of type int

HDL IO
_getIpCoreIntfClass()[source]
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.fifoDrop.FifoWriterDropableAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]

Bases: FifoWriterAgent

get_data()[source]
set_data(d)[source]
hwtLib.mem.fifoDrop._example_FifoDrop()[source]

hwtLib.mem.hashTableCore module

class hwtLib.mem.hashTableCore.HashTableCore(polynome)[source]

Bases: Unit

Generic hash table, in block RAM there is a input key which is hashed ad this has is used as an index into memory item on this place is checked and returned on “lookupRes” interface (item does have to be found, see “found” flag in LookupResultIntf)

memory is an array of items in format

struct item {
    bool item_vld;
    data_t data;
    key_t key;
};
Variables

  • ~.ITEMS_CNT – number of items in memory of hash table

  • ~.KEY_WIDTH – width of the key used by hash table

  • ~.DATA_WIDTH – width of data, can be zero and then no data interface is instantiated

  • ~.LOOKUP_ID_WIDTH – width of id signal for lookup (tag used only by parent component to mark this lookup for later result processing, can be 0)

  • ~.LOOKUP_HASH – flag if lookup interface should have hash signal

  • ~.LOOKUP_KEY – flag if lookup interface should have key signal

  • ~.POLYNOME – polynome for crc hash used in this table

_images/HashTableCore.png
HDL params

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO
HDL components
schematic
__init__(polynome)[source]
_declr_common()[source]
insertLogic(ramW: AddrDataHs)[source]
lookupLogic(ramR: RamHsR)[source]
parseItem(sig)[source]

Parse data stored in hash table

hwtLib.mem.hashTableCore._example_HashTableCore()[source]

hwtLib.mem.hashTableCoreWithRam module

class hwtLib.mem.hashTableCoreWithRam.HashTableCoreWithRam(polynome)[source]

Bases: HashTableCore

HDL params

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO
HDL components
schematic
hwtLib.mem.hashTableCoreWithRam._example_HashTableCoreWithRam()[source]

hwtLib.mem.hashTable_intf module

class hwtLib.mem.hashTable_intf.HashTableIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Interface

HDL params

  • ITEMS_CNT - default value 32 of type int

  • KEY_WIDTH - default value 16 of type int

  • DATA_WIDTH - default value 8 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.HashTableIntfAgent(sim: HdlSimulator, intf: HashTableIntf)[source]

Bases: AgentBase

__init__(sim: HdlSimulator, intf: HashTableIntf)[source]
getDrivers()[source]

Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]

Called before simulation to collect all monitors of interfaces from this agent

class hwtLib.mem.hashTable_intf.InsertIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakeSync

HDL params

  • HASH_WIDTH - default value 8 of type int

  • KEY_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 0 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.InsertIntfAgent(sim: HdlSimulator, intf: InsertIntf)[source]

Bases: HandshakedAgent

Simulation agent for .InsertIntf interface

data format:

  • if interface has data signal, data format is tuple (hash, key, data, item_vld)

  • if interface does not have data signal, data format is tuple (hash, key, item_vld)

__init__(sim: HdlSimulator, intf: InsertIntf)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.hashTable_intf.LookupKeyIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakeSync

HDL params

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • KEY_WIDTH - default value 8 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.LookupKeyIntfAgent(sim: HdlSimulator, intf: LookupKeyIntf)[source]

Bases: HandshakedAgent

Simulation agent for LookupKeyIntf interface

__init__(sim: HdlSimulator, intf: LookupKeyIntf)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.mem.hashTable_intf.LookupResultIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Handshaked

Interface for result of lookup in hash table

Variables

  • ~.HASH_WIDTH – width of the hash used by hash table

  • ~.KEY_WIDTH – width of the key used by hash table

  • ~.LOOKUP_HASH – flag if this interface should have hash signal

  • ~.LOOKUP_KEY – flag if this interface should have hash signal

  • ~.hash – hash for this key (= index in this table)

  • ~.key – original key which was searched for

  • ~.data – data under this key

  • ~.occupied – flag which tells if there is an valid item under this key

HDL params

  • HASH_WIDTH - default value 8 of type int

  • KEY_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 0 of type int

  • LOOKUP_ID_WIDTH - default value 0 of type int

  • LOOKUP_HASH - default value False of type bool

  • LOOKUP_KEY - default value False of type bool

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.hashTable_intf.LookupResultIntfAgent(sim, intf)[source]

Bases: HandshakedAgent

Simulation agent for .LookupResultIntf data is stored in .data data format is tuple (hash, key, data, found) but some items can be missing depending on configuration of interface

__init__(sim, intf)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwtLib.mem.lutRam module

class hwtLib.mem.lutRam.RAM64X1S(hdl_name_override: Optional[str] = None)

Bases: Unit

hwtLib.mem.lutRam.mkLutRamCls(DATA_WIDTH)[source]

Lut ram generator, hdl code will be excluded from serialization because we expect vendor library to contains it

hwtLib.mem.ram module

class hwtLib.mem.ram.RamMultiClock(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

RAM where each port has an independet clock. It can be configured to true dual port RAM etc. It can also be configured to have write mask or to be composed from multiple smaller memories.

HDL params

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value 2 of type int

  • HAS_BE - default value False of type bool

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

HDL IO
schematic
PORT_CLS

alias of BramPort

class hwtLib.mem.ram.RamSingleClock(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

RAM/ROM with only one clock signal. It can be configured to have arbitrary number of ports. It can also be configured to have write mask or to be composed from multiple smaller memories.

HDL params

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value 1 of type intParam which specifies number of ram ports, it can be int or tuple of READ_WRITE, WRITE, READ to specify rw access for each port separately

  • HAS_BE - default value False of type boolParam, if True the write ports will have byte enable signal

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

HDL IO
schematic
PORT_CLS

alias of BramPort_withoutClk

_declr_children()[source]
_declr_ports()[source]
static connect_port(clk: RtlSignal, port: BramPort_withoutClk, mem: RtlSignal)[source]
delegate_to_children()[source]
static mem_write(mem, port: BramPort_withoutClk)[source]

hwtLib.mem.ramCumulativeMask module

class hwtLib.mem.ramCumulativeMask.BramPort_withReadMask_withoutClk(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: BramPort_withoutClk

Block RAM port with a en handshaked interface for arbitration

Variables

  • do_accumulate – Signal if 1 the mask bits are or-ed together with the value in stored in ram

  • do_overwrite – Signal if 1 the the data mask in ram is set to current we value

  • dout_mask – Read port contains this signal which contains the cumulative validity mask for the data.

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • HAS_R - default value True of type bool

  • HAS_W - default value True of type bool

  • HAS_BE - default value False of type bool

HDL IO
class hwtLib.mem.ramCumulativeMask.RamCumulativeMask(hdl_name_override: Optional[str] = None)[source]

Bases: RamSingleClock

RAM which stores also byte enable value for each data word (to keep track of which bytes were updated).

Note

BramPort_withReadMask_withoutClk contains the informations about how to control this component.

PORT_CLS

alias of BramPort_withReadMask_withoutClk

hwtLib.mem.ramCumulativeMask.is_mask_byte_unaligned(mask_signal: RtlSignal) → RtlSignal[source]

hwtLib.mem.ramTransactional module

class hwtLib.mem.ramTransactional.RamTransactional(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

A RAM with 1 read port and 1 write port with flush before functionality. If the flush is activate the current data is read first before it is overwritten by write data. This memory supports multiword transaction and the swap, read and write is atomic in relation with other transactions.

_images/RamTransactional.png
HDL params

  • ADDR_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 8 of type int

  • WORD_WIDTH - default value 16 of type int

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • W_PRIV_T - default value None of type None

  • R_ID_WIDTH - default value 0 of type int

HDL IO
HDL components
schematic
_declr_io()[source]
construct_r_meta(flush_req: RtlSignal, read_pending: RtlSignal, r: RamHsR, w: AddrDataHs, w_index: StructIntf, r_index_o: StructIntf) → HandshakedReg[source]
construct_ram_io() → Tuple[RamHsR, AddrDataHs][source]
construct_read_part(r: TransRamHsR, w_addr: RtlSignal, da_r: RamHsR, r_meta: List[HandshakedReg], flush_req: RtlSignal, read_pending: RtlSignal, r_index_o: StructIntf, r_index_i: StructIntf, flush_data: TransRamHsW)[source]
construct_write_part(w: TransRamHsW, da_r: RamHsR, da_w: AddrDataHs, w_index_i: StructIntf, w_index_o, r_index_o, r_meta_din: HsStructIntf)[source]

hwtLib.mem.ramTransactional_io module

class hwtLib.mem.ramTransactional_io.TransRamHsR(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Interface

Handshaked RAM port

HDL params

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

  • ID_WIDTH - default value 0 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsR_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: HandshakeSync

HDL params

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsW(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Interface

HDL params

  • DATA_WIDTH - default value 64 of type int

  • USE_STRB - default value True of type bool

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

  • USE_FLUSH - default value True of type bool

HDL IO
_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.mem.ramTransactional_io.TransRamHsW_addr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: TransRamHsR_addr

HDL params

  • PRIV_T - default value None of type None

  • ADDR_WIDTH - default value 32 of type int

  • USE_FLUSH - default value True of type bool

HDL IO
_initSimAgent(sim: HdlSimulator)[source]

hwtLib.mem.ramXor module

class hwtLib.mem.ramXor.RamXorSingleClock(hdl_name_override: Optional[str] = None)[source]

Bases: RamSingleClock

Multiport XOR based RAM with only one clock signal

HDL params

  • ADDR_WIDTH - default value 10 of type int

  • DATA_WIDTH - default value 64 of type int

  • PORT_CNT - default value (‘WRITE’, ‘WRITE’, ‘READ’) of type tuple

  • HAS_BE - default value False of type bool

  • MAX_BLOCK_DATA_WIDTH - default value None of type None

  • INIT_DATA - default value None of type None

  • PRIMITIVE_MEMORY_PORTS - default value (‘WRITE’, ‘READ’) of type tuple

HDL IO
HDL components
schematic