hwtLib.peripheral.i2c package

Submodules

hwtLib.peripheral.i2c.intf module

class hwtLib.peripheral.i2c.intf.I2c(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

I2C interface also known as IIC, TWI or Two Wire

If interface is outside of chip it needs pull-up resistors

HDL IO:

• scl - of type hwt.hwIOs.hwIOTristate.HwIOTristateClk with dtype=<HBits, 1bit> - UNKNOWN

• sda - of type hwt.hwIOs.hwIOTristate.HwIOTristateSig - UNKNOWN

__annotations__ = {}

_getIpCoreIntfClass()

_initSimAgent(sim: HdlSimulator)

class hwtLib.peripheral.i2c.intf.IP_IIC

Bases: IntfIpMeta

__annotations__ = {}

__init__()

library

name

vendor

version

hwtLib.peripheral.i2c.masterBitCntrl module

class hwtLib.peripheral.i2c.masterBitCntrl.I2cBitCntrlCmd(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIODataRd

HDL IO:

• din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• cmd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - UNKNOWN

• rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}

_initSimAgent(sim: HdlSimulator)

class hwtLib.peripheral.i2c.masterBitCntrl.I2cBitCntrlCmdAgent(sim: HdlSimulator, hwIO: HwIODataRd, allowNoReset=True)

Bases: HwIODataRdAgent

__annotations__ = {}

get_data()

extract data from interface

set_data(data)

write data to interface

class hwtLib.peripheral.i2c.masterBitCntrl.I2cMasterBitCtrl(hdlName: str | None = None)

Bases: HwModule

Translate simple commands into SCL/SDA transitions Each command has 5 states, 0/1/2/3/idle

start:    SCL  ~~~~~~~~~~~~~~\___
          SDA  XX/~~~~~~~\_______
               x | 0 | 1 | 2 | 3 | i

repstart  SCL  ______/~~~~~~~\___
          SDA  __/~~~~~~~\_______
               x | 0 | 1 | 2 | 3 | i

stop      SCL  _______/~~~~~~~~~~~
          SDA  ==\__________/~~~~
               x | 0 | 1 | 2 | 3 | i

write    SCL  ______/~~~~~~~\____
         SDA  XXX===============XX
              x | 0 | 1 | 2 | 3 | i

read     SCL  ______/~~~~~~~\___
         SDA  XXXXXXX=XXXXXXXXXXX
              x | 0 | 1 | 2 | 3 | i

Timing:	Normal mode	Fast mode
Fscl	100KHz	400KHz
Th_scl	4.0us	0.6us High period of SCL
Tl_scl	4.7us	1.3us Low period of SCL
Tsu:sta	4.7us	0.6us setup time for a repeated start condition
Tsu:sto	4.0us	0.6us setup time for a stop condition
Tbuf	4.7us	1.3us Bus free time between a stop and start condition

HDL params:

• CLK_CNTR_WIDTH - default value 16 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• clk_cnt_initVal - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - SLAVE

• i2c - of type hwtLib.peripheral.i2c.intf.I2c - MASTER

• cntrl - of type hwtLib.peripheral.i2c.masterBitCntrl.I2cBitCntrlCmd - SLAVE

• arbitrationLost - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

• dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic

__annotations__ = {}

arbitrationLostDriver(st, sda, sda_chk, sda_t, stopCond, stateClkEn)

aribitration lost when:

1. master drives SDA high, but the i2c bus is low

2. stop detected while not requested (detect during ‘idle’ state)

detectStartAndStop(scl, sda, scl_t)

Attention:

also dout driver

filter(name, sig)

attempt to remove glitches

stateClkGen(scl_sync, scl_t, scl)

hwtLib.peripheral.i2c.masterBitCntrl.hasFallen(last, actual)

hwtLib.peripheral.i2c.masterBitCntrl.hasRisen(last, actual)