hwtLib.peripheral.mdio package

Submodules

hwtLib.peripheral.mdio.intf module

class hwtLib.peripheral.mdio.intf.IP_mdio

Bases: IntfIpMeta

__annotations__ = {}

__init__()

library

name

vendor

version

class hwtLib.peripheral.mdio.intf.Mdio(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

Management Data Input/Output (MDIO), also known as Serial Management HwIO (SMI) or Media Independent HwIO Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent HwIO,

• MDIO packet format: <PRE><ST><OP><PA><RA><TA><D>

  • PRE: 32b preamble

  • ST: 2b start field

  • OP: 2b operation code

  • PA: 5b PHY address

  • RA: 5b register address

  • TA: 2b turn arround

  • D 16b data

HDL params:

• CLK_FREQ - default value 2500000 of type int

HDL IO:

• c - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN

• io - of type hwt.hwIOs.hwIOTristate.HwIOTristateSig - UNKNOWN

ADDR_BLOCK_W = 14

DEFAULT_FREQ = 2500000

D_W = 16

class OP

Bases: object

READ = 2

WRITE = 1

OP_W = 2

PA_W = 5

PRE = <HBitsConst b32 4294967295>

PRE_W = 32

RA_W = 5

ST = <HBitsConst b2 1>

ST_W = 2

TA = <HBitsConst b2 2>

TA_W = 2

__annotations__ = {}

_getIpCoreIntfClass()

_initSimAgent(sim: HdlSimulator)

class hwtLib.peripheral.mdio.intf.MdioAgent(sim: HdlSimulator, hwIO, allowNoReset=False)

Bases: SyncAgentBase

PULL = 1

__annotations__ = {}

__init__(sim: HdlSimulator, hwIO, allowNoReset=False)

Parameters:

rst – tuple (rst signal, rst_negated flag)

getMonitors()

Note:

use only before running simulator

on_read(phyaddr, regaddr)

on_write(phyaddr, regaddr, data)

reset_state()

rx_bits()

Receive bit from io tristate signal on rising edge of c clock

tx_bits()

Transmit bit to io tristate signal on falling edge of c clock

unpack_addr(rx_bits) → Tuple[int, int, int]

hwtLib.peripheral.mdio.intf.pop_int(bits: Deque[int], bit_cnt: int)

hwtLib.peripheral.mdio.master module

class hwtLib.peripheral.mdio.master.MdioAddr(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

HDL IO:

• phy - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits> - UNKNOWN

• reg - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits> - UNKNOWN

__annotations__ = {}

class hwtLib.peripheral.mdio.master.MdioMaster(hdlName: str | None = None)

Bases: HwModule

Master for MDIO interface.

Variables:

• ~.CLK_FREQ – frequency of input clock

• ~.MDIO_FREQ – frequency of output MDIO clock

• based on:

  • https://opencores.org/websvn/filedetails?repname=ethmac10g&path=%2Fethmac10g%2Ftrunk%2Frtl%2Fverilog%2Fmgmt%2Fmdio.v

  • https://github.com/NetFPGA/netfpga/blob/master/lib/verilog/core/io/mdio/src/nf2_mdio.v

HDL params:

• CLK_FREQ - default value 100000000 of type int

• MDIO_FREQ - default value 2500000 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• md - of type hwtLib.peripheral.mdio.intf.Mdio - MASTER

• rdata - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

• req - of type hwtLib.peripheral.mdio.master.MdioReq - SLAVE

schematic

__annotations__ = {}

_packet_sequence_timer(mdio_clk_rising: HBitsRtlSignal, mdio_clk_falling: HBitsRtlSignal, rst: HBitsRtlSignal)

Create timers for all important events in protocol main FSM

class hwtLib.peripheral.mdio.master.MdioReq(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIORdVldSync

MDIO transaction request interface

HDL IO:

• opcode - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN

• addr - of type hwtLib.peripheral.mdio.master.MdioAddr - UNKNOWN

• wdata - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - UNKNOWN

• vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• rd - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

__annotations__ = {}

_initSimAgent(sim: HdlSimulator)

class hwtLib.peripheral.mdio.master.MdioReqAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)

Bases: HwIODataRdVldAgent

Simulation agent for MdioReq interface

__annotations__ = {}

get_data()

extract data from interface

set_data(data)

write data to interface

hwtLib.peripheral.mdio.master.shift_in_msb_first(reg, sig_in)

Shift data in to register, MSB first