hwtLib.peripheral.mdio package¶
Submodules¶
hwtLib.peripheral.mdio.intf module¶
- class hwtLib.peripheral.mdio.intf.IP_mdio[source]¶
Bases:
IntfIpMeta
- library¶
- name¶
- vendor¶
- version¶
- class hwtLib.peripheral.mdio.intf.Mdio(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
Management Data Input/Output (MDIO), also known as Serial Management Interface (SMI) or Media Independent Interface Management (MIIM), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface,
MDIO packet format: <PRE><ST><OP><PA><RA><TA><D>
PRE: 32b preamble
ST: 2b start field
OP: 2b operation code
PA: 5b PHY address
RA: 5b register address
TA: 2b turn arround
D 16b data
- HDL params
FREQ - default value 2500000 of type int
- HDL IO
c - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - MASTER
io - of type hwt.interfaces.tristate.TristateSig - MASTER
- ADDR_BLOCK_W = 14¶
- DEFAULT_FREQ = 2500000¶
- D_W = 16¶
- OP_W = 2¶
- PA_W = 5¶
- PRE = <BitsVal 4294967295>¶
- PRE_W = 32¶
- RA_W = 5¶
- ST = <BitsVal 1>¶
- ST_W = 2¶
- TA = <BitsVal 2>¶
- TA_W = 2¶
- class hwtLib.peripheral.mdio.intf.MdioAgent(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
Bases:
SyncAgentBase
- PULL = 1¶
- __init__(sim: HdlSimulator, intf, allowNoReset=False)[source]¶
- Parameters
rst – tuple (rst signal, rst_negated flag)
hwtLib.peripheral.mdio.master module¶
- class hwtLib.peripheral.mdio.master.MdioAddr(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
Interface
- HDL IO
phy - of type hwt.interfaces.std.Signal with dtype=<Bits, 5bits> - MASTER
reg - of type hwt.interfaces.std.Signal with dtype=<Bits, 5bits> - MASTER
- class hwtLib.peripheral.mdio.master.MdioMaster(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Master for MDIO interface.
- Variables
~.FREQ – frequency of input clock
~.MDIO_FREQ – frequency of output MDIO clock
- HDL params
FREQ - default value 100000000 of type int
MDIO_FREQ - default value 2500000 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
md - of type hwtLib.peripheral.mdio.intf.Mdio - MASTER
rdata - of type hwt.interfaces.std.Handshaked - MASTER
req - of type hwtLib.peripheral.mdio.master.MdioReq - SLAVE
- class hwtLib.peripheral.mdio.master.MdioReq(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
MDIO transaction request interface
- HDL IO
opcode - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - MASTER
addr - of type hwtLib.peripheral.mdio.master.MdioAddr - MASTER
wdata - of type hwt.interfaces.std.Signal with dtype=<Bits, 16bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
- class hwtLib.peripheral.mdio.master.MdioReqAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶
Bases:
HandshakedAgent
Simulation agent for
MdioReq
interface