hwtLib.peripheral.ethernet package¶

https://github.com/alexforencich/verilog-ethernet/tree/master/rtl https://github.com/jsyk/miilink/tree/master/fpga/src https://github.com/enjoy-digital/liteeth

Submodules¶

hwtLib.peripheral.ethernet.constants module¶

class hwtLib.peripheral.ethernet.constants.ETH[source]¶

Bases: object

PREAMBLE = <HBitsConst b56 24019198012642645>¶

PREAMBLE_1B = <HBitsConst b8 85>¶

SFD = <HBitsConst b8 213>¶

class hwtLib.peripheral.ethernet.constants.ETH_BITRATE[source]¶

Bases: object

M_100G = 6¶

M_100M = 1¶

M_10G = 4¶

M_10M = 0¶

M_1G = 2¶

M_1T = 9¶

M_200G = 7¶

M_25G = 5¶

M_2_5G = 3¶

M_400G = 8¶

get_siganl_width(max_mode: int)[source]¶

hwtLib.peripheral.ethernet.gmii module¶

class hwtLib.peripheral.ethernet.gmii.Gmii(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

Gigabit media independent interface Used to connect 1G Ethernet MAC and PHY

Note:: There is also variant with GTX_CLK, this version uses only single TX clock provided from MAC to PHY

__annotations__ = {}¶

_getIpCoreIntfClass()[source]¶

class hwtLib.peripheral.ethernet.gmii.GmiiRxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
dv - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
er - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

class hwtLib.peripheral.ethernet.gmii.GmiiTxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
er - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

class hwtLib.peripheral.ethernet.gmii.IP_Gmii[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

hwtLib.peripheral.ethernet.mac module¶

class hwtLib.peripheral.ethernet.mac.EthernetMac(hdlName: str | None = None)[source]¶

Bases: HwModule

Media independent Ethernet MAC (Media Access Control) Manages frame dropping, error handling and FCSs, rest (preamble, SFD, IPG, CDCs, PHY signal protocol, …) is managed by adapter for specified PHY interface.

HDL params:

CLK_FREQ - default value 100000000 of type int
BITRATE - default value 1 of type int
DATA_WIDTH - default value 8 of type int
DEFAULT_MAC_ADDR - default value 01:23:45:67:89:AB of type str
HAS_TX - default value True of type bool
HAS_RX - default value True of type bool
RX_FIFO_DEPTH - default value 2048 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
phy_tx - of type hwtLib.amba.axi4s.Axi4Stream - MASTER
phy_rx - of type hwtLib.peripheral.ethernet.vldsynced_data_err_last.VldSyncedDataErrLast - SLAVE
eth - of type hwtLib.amba.axi4s_fullduplex.Axi4StreamFullDuplex - SLAVE

HDL components:

rx_mac_parser - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
tx_fcs_cutter - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
rx_crc - of type hwtLib.logic.crc.Crc
rx_out_fifo - of type hwtLib.amba.axis_comp.fifoDrop.Axi4SFifoDrop
gen_dataOut_fifo_0 - of type hwtLib.amba.axis_comp.fifo.Axi4SFifo
rx_mac_filter - of type hwtLib.peripheral.ethernet._axis_eq.Axi4S_eq
tx_crc - of type hwtLib.logic.crc.Crc
tx_frame_gen - of type hwtLib.amba.axis_comp.frame_deparser._deparser.Axi4S_frameDeparser

schematic

__annotations__ = {}¶

_rx_logic()[source]¶

Recieving of a frame takes at least these steps: * parse dst mac * check fcs * cut off fcs * store in output buffer

The frame can be dropped if: * there is an error durig recieving on PHY/adapter layer (err_rx_phy) * or because of backpressure from eth.rx (err_rx_out_of_mem) * or because of incorrect FCS (err_rx_bad_fcs) * or because of MAC address filter (err_rx_not_my_mac)

_rx_mac_filter()[source]¶

_tx_logic()[source]¶: Compute and append FCS, underflow error checking

hwtLib.peripheral.ethernet.mac.vldSyncedReg(parent: HwModule, hwIO: HwIOVldSync)[source]¶

hwtLib.peripheral.ethernet.mii module¶

class hwtLib.peripheral.ethernet.mii.IP_Mii[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

class hwtLib.peripheral.ethernet.mii.Mii(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

Media Independent HwIO

PHY-MAC interface for <=100BASE Ethernet

HDL IO:

rx_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
rx - of type hwtLib.peripheral.ethernet.mii.MiiRxChannel - UNKNOWN (Master=IN)
tx_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
tx - of type hwtLib.peripheral.ethernet.mii.MiiTxChannel - UNKNOWN

__annotations__ = {}¶

_getIpCoreIntfClass()[source]¶

class hwtLib.peripheral.ethernet.mii.MiiRxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
dv - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
er - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

class hwtLib.peripheral.ethernet.mii.MiiTxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
er - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

hwtLib.peripheral.ethernet.rgmii module¶

class hwtLib.peripheral.ethernet.rgmii.IP_Rgmii[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

class hwtLib.peripheral.ethernet.rgmii.Rgmii(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

Reduced Gigabit Media Independent interface Used to off-chip commect 1G Ethernet MAC and PHY

HDL params:

CLK_FREQ - default value 125000000 of type int

HDL IO:

rx - of type hwtLib.peripheral.ethernet.rgmii.RgmiiChannel - UNKNOWN (Master=IN)
tx - of type hwtLib.peripheral.ethernet.rgmii.RgmiiChannel - UNKNOWN

__annotations__ = {}¶

_getIpCoreIntfClass()[source]¶

class hwtLib.peripheral.ethernet.rgmii.RgmiiChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL params:

CLK_FREQ - default value 125000000 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN
d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN
ctl - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

hwtLib.peripheral.ethernet.rmii module¶

class hwtLib.peripheral.ethernet.rmii.IP_Rmii[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

class hwtLib.peripheral.ethernet.rmii.Rmii(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

Reduced Media Independent HwIO

off-chip PHY-MAC interface for <=100BASE Ethernet

Variables:

~.crs_dc – carrier sense/ rx data valid
~.md – interface for configuration and identification of PHY

HDL params:

CLK_MASTER_DIR - default value DIRECTION.IN of type ipCorePackager.constants.DIRECTION
CLK_FREQ - default value 50000000 of type int
DATA_WIDTH - default value 2 of type int

HDL IO:

ref_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)
tx - of type hwtLib.peripheral.ethernet.rmii.RmiiTxChannel - UNKNOWN
rx - of type hwtLib.peripheral.ethernet.rmii.RmiiRxChannel - UNKNOWN (Master=IN)

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.ethernet.rmii.RmiiRxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN
crs_dv - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.ethernet.rmii.RmiiTxChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - UNKNOWN
en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

hwtLib.peripheral.ethernet.rmii_adapter module¶

class hwtLib.peripheral.ethernet.rmii_adapter.RmiiAdapter(hdlName: str | None = None)[source]¶

Bases: HwModule

Convertor which converts RMII interface to a simple Axi4Stream/VldSynced interface

Variables:

~.CLK_FREQ – specifies the clk.FREQ for this core, f None it means that clk and eth.ref_clk is the same signal and synchronisation is not required
~.ASYNC_BUFF_DEPTH – depth of asynchronous buffers between eth.ref_clk clock domain and clk domain (if set to None the clock domain has to be the same)

HDL params:

CLK_FREQ - default value None of type None
ASYNC_BUFF_DEPTH - default value None of type None

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
eth - of type hwtLib.peripheral.ethernet.rmii.Rmii - MASTER
tx - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE
rx - of type hwtLib.peripheral.ethernet.vldsynced_data_err_last.VldSyncedDataErrLast - MASTER

schematic

__annotations__ = {}¶

_rx_logic(rmii: Rmii, rx: VldSyncedDataErrLast, D_W: int, RMII_W: int, clk_edge)[source]¶

_tx_ipg_logic(clk_edge, tx: Axi4Stream, tx_last_bits: RtlSignal, RMII_W)[source]¶: Tx IPG (Inter Packet Gap) logic, wait 96 bit times before sending next packet

_tx_logic(rmii: Rmii, tx: Axi4Stream, D_W: int, RMII_W: int, clk_edge)[source]¶

hwtLib.peripheral.ethernet.rmii_agent module¶

class hwtLib.peripheral.ethernet.rmii_agent.RmiiAgent(sim: HdlSimulator, hwIO)[source]¶

Bases: AgentBase

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO)[source]¶

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

class hwtLib.peripheral.ethernet.rmii_agent.RmiiRxChannelAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]¶

Bases: HwIODataVldAgent

Simulation agent for hwtLib.peripheral.ethernet.rmii.RmiiRxChannel interface

__annotations__ = {}¶

_append_frame(frame: List[int], add_preamble=True)[source]¶

get_data()[source]¶

get_valid()[source]¶

classmethod get_valid_signal(hwIO)[source]¶

set_data(data)[source]¶

set_valid(val)[source]¶

class hwtLib.peripheral.ethernet.rmii_agent.RmiiTxChannelAgent(sim: HdlSimulator, hwIO: RmiiTxChannel, allowNoReset=False)[source]¶

Bases: HwIODataVldAgent

Simulation agent for hwtLib.peripheral.ethernet.rmii.RmiiTxChannel interface

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO: RmiiTxChannel, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

_pop_frame()[source]¶

getMonitors()[source]¶

Note:: use only before running simulator

get_data()[source]¶

get_valid()[source]¶

classmethod get_valid_signal(hwIO)[source]¶

set_data(data)[source]¶

set_valid(val)[source]¶

hwtLib.peripheral.ethernet.vldsynced_data_err_last module¶

class hwtLib.peripheral.ethernet.vldsynced_data_err_last.VldSyncedDataErrLast(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIODataVld

Interface with data, vld, err, last signal

HDL params:

DATA_WIDTH - default value 64 of type int

HDL IO:

data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN
vld - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
mask - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN
err - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN
last - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}¶

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.peripheral.ethernet.vldsynced_data_err_last.VldSyncedDataErrLastAgent(sim: HdlSimulator, hwIO, allowNoReset=False)[source]¶

Bases: HwIODataVldAgent

__annotations__ = {}¶

__init__(sim: HdlSimulator, hwIO, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

get_data()[source]¶

set_data(data)[source]¶

hwtLib.peripheral.ethernet.xgmii module¶

class hwtLib.peripheral.ethernet.xgmii.IP_xgmii[source]¶

Bases: IntfIpMeta

__annotations__ = {}¶

__init__()[source]¶

library¶

name¶

vendor¶

version¶

class hwtLib.peripheral.ethernet.xgmii.Xgmii(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

10G Media Independent HwIO

HDL params:

DATA_WIDTH - default value 64 of type int
CLK_FREQ - default value 156250000 of type int
IS_DDR - default value True of type bool
ALIGNMENT - default value 1 of type int

HDL IO:

rx - of type hwtLib.peripheral.ethernet.xgmii.XgmiiChannel - UNKNOWN (Master=IN)
tx - of type hwtLib.peripheral.ethernet.xgmii.XgmiiChannel - UNKNOWN

__annotations__ = {}¶

class hwtLib.peripheral.ethernet.xgmii.XgmiiChannel(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]¶

Bases: HwIO

Variables:

~.clk – clock signal
~.d – data signal
~.c – control signal
~.IS_DDR – if True, the clock is used as double-data-rate clock (read/write data on rising and falling edge of clk)
~.ALIGNMENT – specifies alignment of the start of the packet 1 means packet can start anywhere 4 for 8B wide interface means that packet can start at lane 0 or 4

HDL params:

DATA_WIDTH - default value 64 of type int
CLK_FREQ - default value 156250000 of type int
IS_DDR - default value True of type bool
ALIGNMENT - default value 1 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - UNKNOWN
d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - UNKNOWN
c - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - UNKNOWN

class CMD[source]¶

Bases: object

This is an enum of values which may appear on data byte while corresponding control bit is CONTROL

ERROR = <HBitsConst b8 254>¶

IDLE = <HBitsConst b8 7>¶

START = <HBitsConst b8 251>¶

TERM = <HBitsConst b8 253>¶

class CONTROL[source]¶

Bases: object

Enum to name meanings of the bit values in “c” signal.

CONTROL = 1¶

DATA = 0¶

__annotations__ = {}¶

detect_control(s) → List[RtlSignal][source]¶

Returns:: a list of signals which are 1 if the specified control signal was detected on that specific byte, detector for byte 0 first in output list