hwtLib.xilinx.ipif package

IPIF (IP IC) interface is simple bus interface used as a service bus in FPGA designs

Submodules

hwtLib.xilinx.ipif.axi4Lite_to_ipif module

class hwtLib.xilinx.ipif.axi4Lite_to_ipif.Axi4Lite_to_Ipif(hdl_name_override: Optional[str] = None)[source]

Bases: BusBridge

Bridge from AxiLite interface to IPIF interface

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
schematic
handleAddr(st)[source]
handleResp()[source]
mainFsm(dataRegR_vld)[source]

hwtLib.xilinx.ipif.buff module

class hwtLib.xilinx.ipif.buff.IpifBuff(hdl_name_override: Optional[str] = None)[source]

Bases: BusBridge

Register or fifo for IPIF interface, used to break critical paths and buffer transactions

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • ADDR_BUFF_DEPTH - default value 1 of type int

  • DATA_BUFF_DEPTH - default value 1 of type int

HDL IO
schematic
connectRegistered(intfFrom, intfTo)[source]

hwtLib.xilinx.ipif.endpoint module

class hwtLib.xilinx.ipif.endpoint.IpifEndpoint(structTemplate, intfCls=<class 'hwtLib.xilinx.ipif.intf.Ipif'>, shouldEnterFn=None)[source]

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
schematic
__init__(structTemplate, intfCls=<class 'hwtLib.xilinx.ipif.intf.Ipif'>, shouldEnterFn=None)[source]
Parameters

  • structTemplate – instance of HStruct which describes address space of this endpoint

  • intfCls – class of bus interface which should be used

  • shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()
Returns

size of one word in unit of address

hwtLib.xilinx.ipif.endpoint._example_IpifEndpoint()[source]

hwtLib.xilinx.ipif.interconnectMatrix module

class hwtLib.xilinx.ipif.interconnectMatrix.IpifInterconnectMatrix(hdl_name_override: Optional[str] = None)[source]

Bases: BusInterconnect

Simple matrix interconnect for IPIF interface

HDL params

  • SLAVES - default value ((0, 256), (256, 256), (<class ‘hwtLib.abstract.busInterconnect.AUTO_ADDR’>, 256), (4096, 4096)) of type tuple

  • MASTERS - default value ({0, 1, 2, 3},) of type tuple

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
schematic
hwtLib.xilinx.ipif.interconnectMatrix._example_IpifInterconnectMatrix()[source]

hwtLib.xilinx.ipif.intf module

class hwtLib.xilinx.ipif.intf.Ipif(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Interface

IPIF - IP interface is interface which was often used in designs for Xilinx FPGAs around year 2012

  • shared address, validity signals, mask, write ack

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

HDL IO
READ = 1
WRITE = 0
_getAddrStep()[source]
Returns

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()[source]
Returns

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)[source]
class hwtLib.xilinx.ipif.intf.IpifAgent(sim: HdlSimulator, intf, allowNoReset=True)[source]

Bases: SyncAgentBase

Variables

  • ~.requests – list of tuples (READ, address) or (WRITE, address, data, mask) used for driver

  • ~.r_data – list of read data for driver

  • ~.mem – if agent is in monitor mode (= is slave) all reads and writes are performed on mem object, index is word index

  • ~.actual – actual request which is performed (in driver mode)

Note

this behavior can be overriden by onRead/onWrite methods

__init__(sim: HdlSimulator, intf, allowNoReset=True)[source]
Parameters

rst – tuple (rst signal, rst_negated flag)

doReq(req)[source]
driver()[source]

Implement this method to drive your interface in simulation/verification

monitor()[source]

Implement this method to monitor your interface in simulation/verification

onRead(addr)[source]
onWrite(addr, val, byteen)[source]
class hwtLib.xilinx.ipif.intf.IpifAgentState(value)[source]

Bases: Enum

An enumeration.

IDLE = 0
READ = 1
WRITE = 2
class hwtLib.xilinx.ipif.intf.IpifWithCE(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: Ipif

HDL params

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • REG_COUNT - default value 1 of type int

HDL IO
_ag: Optional[AgentBase]
_associatedClk: Optional[Interface]
_associatedRst: Optional[Interface]
_ctx: Optional[RtlNetlist]
_direction: INTF_DIRECTION
_hdl_port: Optional[HdlPortItem]
_masterDir: DIRECTION
_name: Optional[str]
_parent: Optional['Unit']
_setAttrListener: Optional[Callable[[str, object], None]]

hwtLib.xilinx.ipif.simMaster module

class hwtLib.xilinx.ipif.simMaster.IPFISimMaster(bus, registerMap)[source]

Bases: AbstractMemSpaceMaster

Controller of IPIF simulation agent which keeps track of transactions and allows struct like data access

_read(addr, size, onDone=None)[source]

Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)[source]

Add write transaction to agent of interface

Parameters

  • addr – address value on bus to write on

  • size – size of data to write in bites

  • data – data to write on bus

  • onDone – on write done callback function(sim) -> None