hwtLib.xilinx.ipif package

IPIF (IP IC) interface is simple bus interface used as a service bus in FPGA designs

• https://www.xilinx.com/support/documentation/ip_documentation/axi_lite_ipif/v3_0/pg155-axi-lite-ipif.pdf

Submodules

hwtLib.xilinx.ipif.axi4Lite_to_ipif module

class hwtLib.xilinx.ipif.axi4Lite_to_ipif.Axi4Lite_to_Ipif(hdlName: str | None = None)

Bases: BusBridge

Bridge from AxiLite interface to IPIF interface

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

• m - of type hwtLib.xilinx.ipif.hIOIpif.Ipif - MASTER

schematic

__annotations__ = {}

handleAddr(st)

handleResp()

mainFsm(dataRegR_vld)

hwtLib.xilinx.ipif.buff module

class hwtLib.xilinx.ipif.buff.IpifBuff(hdlName: str | None = None)

Bases: BusBridge

Register or FIFO for IPIF interface, used to break critical paths and buffer transactions

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• ADDR_BUFF_DEPTH - default value 1 of type int

• DATA_BUFF_DEPTH - default value 1 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.xilinx.ipif.hIOIpif.Ipif - SLAVE

• m - of type hwtLib.xilinx.ipif.hIOIpif.Ipif - MASTER

schematic

__annotations__ = {}

connectRegistered(hwIOFrom: Ipif, hwIOTo: Ipif)

hwtLib.xilinx.ipif.endpoint module

class hwtLib.xilinx.ipif.endpoint.IpifEndpoint(structTemplate, hwIOCls=<class 'hwtLib.xilinx.ipif.hIOIpif.Ipif'>, shouldEnterFn=None)

Bases: BusEndpoint

Delegate request from bus to fields of structure

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• bus - of type hwtLib.xilinx.ipif.hIOIpif.Ipif - SLAVE

• decoded - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 32bits, unsigned> field0 <HBits, 32bits, unsigned> field1 <HBits, 32bits, unsigned>[32] bramMapped } - MASTER

schematic

__annotations__ = {}

__init__(structTemplate, hwIOCls=<class 'hwtLib.xilinx.ipif.hIOIpif.Ipif'>, shouldEnterFn=None)

Parameters:

• structTemplate – instance of HStruct which describes address space of this endpoint

• hwIOCls – class of bus interface which should be used

• shouldEnterFn – function(root_t, structFieldPath) return (shouldEnter, shouldUse) where shouldEnter is flag that means iterator over this interface should look inside of this actual object and shouldUse flag means that this field should be used (to create interface)

_getAddrStep()

Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()

Returns:

size of one word in unit of address

hwtLib.xilinx.ipif.endpoint._example_IpifEndpoint()

hwtLib.xilinx.ipif.hIOIpif module

class hwtLib.xilinx.ipif.hIOIpif.Ipif(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: HwIO

IPIF - IP interface is interface which was often used in designs for Xilinx FPGAs around year 2012

• shared address, validity signals, mask, write ack

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO:

• bus2ip_cs - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• bus2ip_rnw - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• bus2ip_addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• bus2ip_data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• bus2ip_be - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

• ip2bus_data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

• ip2bus_wrack - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• ip2bus_rdack - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• ip2bus_error - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

READ = 1

WRITE = 0

__annotations__ = {}

_getAddrStep()

Returns:

how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)

_getWordAddrStep()

Returns:

size of one word in unit of address

_initSimAgent(sim: HdlSimulator)

class hwtLib.xilinx.ipif.hIOIpif.IpifAgent(sim: HdlSimulator, hwIO, allowNoReset=True)

Bases: SyncAgentBase

Variables:

• ~.requests – list of tuples (READ, address) or (WRITE, address, data, mask) used for driver

• ~.r_data – list of read data for driver

• ~.mem – if agent is in monitor mode (= is slave) all reads and writes are performed on mem object, index is word index

• ~.actual – actual request which is performed (in driver mode)

Note:

this behavior can be overridden by onRead/onWrite methods

__annotations__ = {}

__init__(sim: HdlSimulator, hwIO, allowNoReset=True)

Parameters:

rst – tuple (rst signal, rst_negated flag)

doReq(req)

driver()

Implement this method to drive your interface in simulation/verification

monitor()

Implement this method to monitor your interface in simulation/verification

onRead(addr)

onWrite(addr, val, byteen)

class hwtLib.xilinx.ipif.hIOIpif.IpifAgentState(*values)

Bases: Enum

IDLE = 0

READ = 1

WRITE = 2

class hwtLib.xilinx.ipif.hIOIpif.IpifWithCE(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)

Bases: Ipif

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

• REG_COUNT - default value 1 of type int

HDL IO:

• bus2ip_cs - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• bus2ip_rnw - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• bus2ip_addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• bus2ip_data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN

• bus2ip_be - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - UNKNOWN

• ip2bus_data - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - UNKNOWN (Master=IN)

• ip2bus_wrack - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• ip2bus_rdack - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• ip2bus_error - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN (Master=IN)

• bus2ip_rdce - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

• bus2ip_wrce - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - UNKNOWN

__annotations__ = {}

hwtLib.xilinx.ipif.interconnectMatrix module

class hwtLib.xilinx.ipif.interconnectMatrix.IpifInterconnectMatrix(hdlName: str | None = None)

Bases: BusInterconnect

Simple matrix interconnect for IPIF interface

HDL params:

• SLAVES - default value ((0, 256), (256, 256), (<class ‘hwtLib.abstract.busInterconnect.AUTO_ADDR’>, 256), (4096, 4096)) of type tuple

• MASTERS - default value ({0, 1, 2, 3},) of type tuple

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

• m - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

schematic

__annotations__ = {}

hwtLib.xilinx.ipif.interconnectMatrix._example_IpifInterconnectMatrix()

hwtLib.xilinx.ipif.simMaster module

class hwtLib.xilinx.ipif.simMaster.IPFISimMaster(bus, registerMap)

Bases: AbstractMemSpaceMaster

Controller of IPIF simulation agent which keeps track of transactions and allows struct like data access

__annotations__ = {}

_read(addr, size, onDone=None)

Add read transaction to agent of interface :param addr: address value on bus to read froms :param size: size of data to read in bites :param onDone: on read done callback function(sim) -> None

_write(addr, size, data, mask, onDone=None)

Add write transaction to agent of interface

Parameters:

• addr – address value on bus to write on

• size – size of data to write in bites

• data – data to write on bus

• onDone – on write done callback function(sim) -> None