hwtLib.xilinx package

Subpackages

• hwtLib.xilinx.ipif package
  • Submodules
  • hwtLib.xilinx.ipif.axi4Lite_to_ipif module
  • hwtLib.xilinx.ipif.buff module
  • hwtLib.xilinx.ipif.endpoint module
  • hwtLib.xilinx.ipif.interconnectMatrix module
  • hwtLib.xilinx.ipif.intf module
  • hwtLib.xilinx.ipif.simMaster module
• hwtLib.xilinx.locallink package
  • Submodules
  • hwtLib.xilinx.locallink.axis_conv module
  • hwtLib.xilinx.locallink.intf module
• hwtLib.xilinx.primitive package
  • Subpackages
    • hwtLib.xilinx.primitive.examples package
      • Submodules
      • hwtLib.xilinx.primitive.examples.dsp48e1Add module
  • Submodules
  • hwtLib.xilinx.primitive.dsp48e1 module
  • hwtLib.xilinx.primitive.dsp48e1_constants module
  • hwtLib.xilinx.primitive.lutAsShiftReg module
  • hwtLib.xilinx.primitive.mmcme2 module

Submodules

hwtLib.xilinx.constants module

hwtLib.xilinx.platform module

class hwtLib.xilinx.platform.XilinxVivadoPlatform(part: Optional[str] = None)

Bases: DummyPlatform

__init__(part: Optional[str] = None)

hwtLib.xilinx.slr_crossing module

class hwtLib.xilinx.slr_crossing.HsSlrCrossing(hdl_name_override: Optional[str] = None)

Bases: HsSlrCrossingIo

Super Logic Region (SLR) crossing for handshaked interfaces

SLR represents one chiplet of FPGA which uses stacked silicon interconnect (SSI) or equivalent. The SLR corssing is required on SLR boundaries to met the timing. The crossing itself is just a pipeline of registers.

class hwtLib.xilinx.slr_crossing.HsSlrCrossingIo(hdl_name_override: Optional[str] = None)

Bases: BusBridge

An abstract class with a declaration of interfaces for handskaked SLR crosings

class hwtLib.xilinx.slr_crossing.SlrCrossingDst(hdl_name_override: Optional[str] = None)

Bases: HsSlrCrossingIo

A part of SLR crossing which should be placed in SLR of consumer

class hwtLib.xilinx.slr_crossing.SlrCrossingSrc(hdl_name_override: Optional[str] = None)

Bases: HsSlrCrossingIo

A part of SLR crossing which should be placed in SLR of producer