hwtLib.amba.axi_comp.sim package

Submodules

hwtLib.amba.axi_comp.sim.ram module

class hwtLib.amba.axi_comp.sim.ram.AxiSimRam(axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None, allow_unaligned_addr=False)

Bases: AxiDpSimRam

Simulation memory for Axi3/4 interfaces (slave component)

__init__(axi=None, axiAR=None, axiR=None, axiAW=None, axiW=None, axiB=None, parent=None, allow_unaligned_addr=False)

Parameters

• clk – clk which should this memory use in simulation

• axi – axi (Axi3/4 master) interface to listen on

• axiB (axiAR, axiR, axiAW, axiW,) – splited interface use this if you do not have full axi interface

• parent – parent instance of this memory, memory will operate with same memory as parent one

Attention

use axi or axi parts not bouth

Attention

memories are commiting into memory in “data” property after transaction is complete

_write_single_word(data: HValue, strb: int, word_i: int)

add_r_ag_data(_id, data, isLast)

doRead()

doWrite()

doWriteAck(_id)

parseReq(req)

pop_w_ag_data(_id)