hwtLib.amba.axi_comp package

Generic Axi3/4 componets

note

majority of componets can be also configured to use Axi3/4Lite interface instead

Submodules

hwtLib.amba.axi_comp.buff module

class hwtLib.amba.axi_comp.buff.AxiBuff(intfCls)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Transaction buffer for AXI3/4/Lite and others

schematic
__init__(intfCls)[source]

Initialize self. See help(type(self)) for accurate signature.

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

static _serializeDecision(parentUnit, priv)

Decide to serialize only objs with uniq parameters and class

Parameters

priv – private data for this function ({frozen_params: obj})

Returns

tuple (do serialize this object, next priv, replacement unit)

hwtLib.amba.axi_comp.buff._example_AxiBuff()[source]

hwtLib.amba.axi_comp.buff_cdc module

class hwtLib.amba.axi_comp.buff_cdc.AxiBuffCdc(intfCls)[source]

Bases: hwtLib.amba.axi_comp.buff.AxiBuff

Clock domain crossing with buffers for AXI3/4/Lite and others

Note

for DEPTH = 1 CDC register is used, else AsyncFifo

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

_setup_clk_rst_n()[source]
hwtLib.amba.axi_comp.buff_cdc._example_AxiBuffCdc()[source]

hwtLib.amba.axi_comp.builder module

class hwtLib.amba.axi_comp.builder.AxiBuilder(parent, srcInterface, name=None, master_to_slave=True)[source]

Bases: hwtLib.abstract.componentBuilder.AbstractComponentBuilder

Helper class wich simplifies instantiation and configuration of common components for Axi interfaces

BuffCdcCls

alias of hwtLib.amba.axi_comp.buff_cdc.AxiBuffCdc

BuffCls

alias of hwtLib.amba.axi_comp.buff.AxiBuff

_genericInstance(unit_cls, name, set_params=<function AxiBuilder.<lambda>>, update_params=True, propagate_clk_rst=True)[source]

Instantiate generic component and connect basics

Parameters
  • unit_cls – class of unit which is being created

  • name – name for unit_cls instance

  • set_params – function which updates parameters as is required (parameters are already shared with self.end interface)

buff(addr_items=1, data_items=1)[source]

Use registers and FIFOs to create buffer of specified paramters

Parameters

items – number of items in buffer

buff_cdc(clk, rst, addr_items=1, data_items=1)[source]

Instanciate a CDC (Clock Domain Crossing) buffer or AsyncFifo on selected interface

Note

if items==1 CDC clock synchronization register is used if items>1 asynchronous FIFO is used

resize(addr_width=None, data_width=None)[source]
to_axi(axi_cls, id_width=0)[source]

hwtLib.amba.axi_comp.resize module

class hwtLib.amba.axi_comp.resize.AxiResize(intfCls)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Change DATA_WIDTH of axi interface

schematic
__init__(intfCls)[source]

Initialize self. See help(type(self)) for accurate signature.

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

connect_shifted(src_ch, dst_ch, i)[source]
connect_with_padding(src, src_range, dst, dst_range)[source]
propagate_addr(m_a, s_a)[source]
select_data_word_from_ouput_word(m, s)[source]
hwtLib.amba.axi_comp.resize._example_AxiResize()[source]

hwtLib.amba.axi_comp.slave_timeout module

class hwtLib.amba.axi_comp.slave_timeout.AxiSlaveTimeout(intfCls)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Component witch has internal timeout for r/b channel and responds with the error code if the slave does not respond in specified time

Note

blocks the overlapping transactions, it allows only a single pending transaction per type

__init__(intfCls)[source]

Initialize self. See help(type(self)) for accurate signature.

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.amba.axi_comp.static_remap module

class hwtLib.amba.axi_comp.static_remap.AxiStaticRemap(intfCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]

Bases: hwtLib.abstract.busStaticRemap.BusStaticRemap

BusStaticRemap implementation for AXI3/4 full/lite interfaces :note: this component only remaps some memory regions, but it does not perform the address checking

schematic
__init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]

Initialize self. See help(type(self)) for accurate signature.

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.amba.axi_comp.static_remap._example_AxiStaticRemap()[source]

hwtLib.amba.axi_comp.stream_to_mem module

class hwtLib.amba.axi_comp.stream_to_mem.Axi4streamToMem[source]

Bases: hwt.synthesizer.unit.Unit

Most simple DMA for AXI4 interface.

  • 0x0 control reg.
    • bit 0, rw - on/off (1 means on)

    • bit 1, r - idle (1 if no transaction in progress)

0x4 baseAddr

Length of written data is specified by DATA_LEN. Input data is splited on smaller frames to fit MAX_BUTST_LEN.

If there is transaction pending idle flag is 0, if on/off is set to 0 in this state unit continues until all data are send and then stays off. This could be use as synchronization with the software.

  1. driver enables this unit, then tests while not idle.

  2. then waits while idle.

  3. then reads the data and back to 1

or unit is enabled and driver disables it only for the time of reading.

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

axiWAddrHandler(st, baseAddr, actualAddr, lenRem)[source]

AXI write addr logic

connectRegisters(st, onoff, baseAddr)[source]

connection of AXI-lite registers

dataWFeed(st, lenRem, actualLenRem)[source]

Connection between din and axi.w channel

mainFsm(st, onoff, lenRem, actualLenRem)[source]
w_allAck(st)[source]

In this clk data word will be transfered

hwtLib.amba.axi_comp.tester module

class hwtLib.amba.axi_comp.tester.AxiTester(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]

Bases: hwt.synthesizer.unit.Unit

Tester for AXI3/4 interfaces

Can precisely control order and timing of read address/write address/read/write/write response transactions Allows to read and specify values of controls signals like cache/lock/burst etc…

schematic
__init__(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>)[source]

Initialize self. See help(type(self)) for accurate signature.

_add_ep()[source]
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.amba.axi_comp.to_axiLite module

class hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite(intfCLs=<class 'hwtLib.amba.axi4.Axi4'>)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

AXI3/4 -> Axi4Lite bridge

Attention

AXI interfaces works in read first mode, overlapping transactions are not checked to end up in proper r/w order

Attention

only last response code on AxiLite for transaction is used as a response code for Axi4 That means if the error appears somewhere in middle beat of the transaction the error is ignored

Variables

MAX_TRANS_OVERLAP – depth of internal FIFO which is used to allow the transactions to overlap each other in order to pipeline the execution of transactions

schematic
__init__(intfCLs=<class 'hwtLib.amba.axi4.Axi4'>)[source]

Initialize self. See help(type(self)) for accurate signature.

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

gen_addr_logic(addr_ch_in: hwtLib.amba.axi4.Axi4_addr, addr_ch_out: hwtLib.amba.axi4Lite.Axi4Lite_addr, req_fifo_inp: hwtLib.amba.axi_comp.to_axiLite.HandshakedIdAndLen)[source]

Instanciate logic which splits the transactions to a beats on AxiLite interface and propagate informations about the transacttions to req_fifo_inp for later use

gen_b_or_r_logic(inp, outp, fifo_out, propagete_only_on_last)[source]

Use counter to skip intermediate generated transactions and pass only confirmation from last beat of the original transaction

gen_w_logic(w_in, w_out)[source]

Directly connect the w channels with ignore of extra signals (The data should be already synchronized by order of beats on channel)

class hwtLib.amba.axi_comp.to_axiLite.HandshakedIdAndLen(masterDir=<DIRECTION.OUT: 1>, loadConfig=True)[source]

Bases: hwt.interfaces.std.HandshakeSync

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well