hwtLib.amba.axi_comp package¶
Generic Axi3/4 componets
- note
majority of componets can be also configured to use Axi3/4Lite interface instead
Subpackages¶
- hwtLib.amba.axi_comp.cache package
- Submodules
- hwtLib.amba.axi_comp.cache.addrTypeConfig module
- hwtLib.amba.axi_comp.cache.cacheWriteAllocWawOnlyWritePropagating module
- hwtLib.amba.axi_comp.cache.lru_array module
- hwtLib.amba.axi_comp.cache.pseudo_lru module
- hwtLib.amba.axi_comp.cache.tag_array module
- hwtLib.amba.axi_comp.cache.utils module
- hwtLib.amba.axi_comp.interconnect package
- Submodules
- hwtLib.amba.axi_comp.interconnect.base module
- hwtLib.amba.axi_comp.interconnect.common module
- hwtLib.amba.axi_comp.interconnect.matrix module
- hwtLib.amba.axi_comp.interconnect.matrixAddrCrossbar module
- hwtLib.amba.axi_comp.interconnect.matrixCrossbar module
- hwtLib.amba.axi_comp.interconnect.matrixR module
- hwtLib.amba.axi_comp.interconnect.matrixW module
- hwtLib.amba.axi_comp.lsu package
- Submodules
- hwtLib.amba.axi_comp.lsu.fifo_oooread module
- hwtLib.amba.axi_comp.lsu.interfaces module
- hwtLib.amba.axi_comp.lsu.read_aggregator module
- hwtLib.amba.axi_comp.lsu.store_queue_write_propagating module
- hwtLib.amba.axi_comp.lsu.write_aggregator module
- hwtLib.amba.axi_comp.lsu.write_aggregator_write_dispatcher module
- hwtLib.amba.axi_comp.oooOp package
- hwtLib.amba.axi_comp.sim package
Submodules¶
hwtLib.amba.axi_comp.buff module¶
- class hwtLib.amba.axi_comp.buff.AxiBuff(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Transaction buffer for AXI3/4/Lite and others
- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
ADDR_BUFF_DEPTH - default value 4 of type int
DATA_BUFF_DEPTH - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER
- HDL components
ar_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
aw_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
w_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
r_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
b_fifo_0 - of type hwtLib.amba.axis_comp.fifo.AxiSFifo
hwtLib.amba.axi_comp.buff_cdc module¶
- class hwtLib.amba.axi_comp.buff_cdc.AxiBuffCdc(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiBuff
Clock domain crossing with buffers for AXI3/4/Lite and others
- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
ADDR_BUFF_DEPTH - default value 5 of type int
DATA_BUFF_DEPTH - default value 5 of type int
M_FREQ - default value 102000000 of type int
S_FREQ - default value 102000000 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER
m_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
m_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
- HDL components
ar_cdcAFifo_0 - of type hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync
aw_cdcAFifo_0 - of type hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync
w_cdcAFifo_0 - of type hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync
r_cdcAFifo_0 - of type hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync
b_cdcAFifo_0 - of type hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync
hwtLib.amba.axi_comp.builder module¶
- class hwtLib.amba.axi_comp.builder.AxiBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)[source]¶
Bases:
AbstractComponentBuilder
Helper class wich simplifies instantiation and configuration of common components for Axi interfaces
- BuffCdcCls¶
alias of
AxiBuffCdc
- _genericInstance(unit_cls, name, set_params=<function AxiBuilder.<lambda>>, update_params=True, propagate_clk_rst=True)[source]¶
Instantiate generic component and connect basics
- Parameters
unit_cls – class of unit which is being created
name – name for unit_cls instance
set_params – function which updates parameters as is required (parameters are already shared with self.end interface)
- buff(addr_items=1, data_items=1)[source]¶
Use registers and FIFOs to create buffer of specified paramters
- Parameters
items – number of items in buffer
hwtLib.amba.axi_comp.resize module¶
- class hwtLib.amba.axi_comp.resize.AxiResize(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Change DATA_WIDTH of axi interface
- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4Lite.Axi4Lite’> of type type
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
OUT_DATA_WIDTH - default value 512 of type int
OUT_ADDR_WIDTH - default value 32 of type int
MAX_TRANS_OVERLAP - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE
m - of type hwtLib.amba.axi4Lite.Axi4Lite - MASTER
- HDL components
gen_aw_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
aw_align_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_ar_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg
ar_align_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
hwtLib.amba.axi_comp.slave_timeout module¶
- class hwtLib.amba.axi_comp.slave_timeout.AxiSlaveTimeout(intfCls, hdl_name_override: Optional[str] = None)[source]¶
Bases:
BusBridge
Component witch has internal timeout for r/b channel and responds with the error code if the slave does not respond in specified time
- HDL params
TIMEOUT - default value 4096 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.amba.axi4.Axi4 - MASTER
hwtLib.amba.axi_comp.static_remap module¶
- class hwtLib.amba.axi_comp.static_remap.AxiStaticRemap(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶
Bases:
BusStaticRemap
BusStaticRemap
implementation for AXI3/4 full/lite interfaces :note: this component only remaps some memory regions, but it does not perform the address checking- HDL params
INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type
MEM_MAP - default value [(0, 4096, 4096), (4096, 4096, 0)] of type list
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
- HDL IO
m - of type hwtLib.amba.axi4.Axi4 - MASTER
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
hwtLib.amba.axi_comp.stream_to_mem module¶
- class hwtLib.amba.axi_comp.stream_to_mem.Axi4streamToMem(hdl_name_override: Optional[str] = None)[source]¶
Bases:
Unit
Most simple DMA for AXI4 interface.
- 0x0 control reg.
bit 0, rw - on/off (1 means on)
bit 1, r - idle (1 if no transaction in progress)
0x4 baseAddr
Length of written data is specified by DATA_LEN. Input data is splited on smaller frames to fit MAX_BUTST_LEN.
If there is transaction pending idle flag is 0, if on/off is set to 0 in this state unit continues until all data are send and then stays off. This could be use as synchronization with the software.
driver enables this unit, then tests while not idle.
then waits while idle.
then reads the data and back to 1
or unit is enabled and driver disables it only for the time of reading.
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 32 of type int
CNTRL_AW - default value 5 of type int
DATA_LEN - default value 33 of type int
MAX_BUTST_LEN - default value 16 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
axi - of type hwtLib.amba.axi4.Axi4 - MASTER
dataIn - of type hwt.interfaces.std.Handshaked - SLAVE
cntrlBus - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE
- HDL components
regsConventor - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint
hwtLib.amba.axi_comp.tester module¶
- class hwtLib.amba.axi_comp.tester.AxiTester(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶
Bases:
Unit
Tester for AXI3/4 interfaces
Can precisely control order and timing of read address/write address/read/write/write response transactions Allows to read and specify values of controls signals like cache/lock/burst etc…
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
CNTRL_DATA_WIDTH - default value 32 of type int
CNTRL_ADDR_WIDTH - default value 32 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
m_axi - of type hwtLib.amba.axi4.Axi4 - MASTER
cntrl - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE
- HDL components
axi_ep - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint
hwtLib.amba.axi_comp.to_axiLite module¶
- class hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶
Bases:
BusBridge
AXI3/4 -> Axi4Lite bridge
- Variables
~.MAX_TRANS_OVERLAP – depth of internal FIFO which is used to allow the transactions to overlap each other in order to pipeline the execution of transactions
- HDL params
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
ID_WIDTH - default value 6 of type int
ADDR_USER_WIDTH - default value 0 of type int
MAX_TRANS_OVERLAP - default value 4 of type int
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
s - of type hwtLib.amba.axi4.Axi4 - SLAVE
m - of type hwtLib.amba.axi4Lite.Axi4Lite - MASTER
- HDL components
r_req_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
w_req_fifo - of type hwtLib.handshaked.fifo.HandshakedFifo
out_reg - of type hwtLib.amba.axi_comp.buff.AxiBuff
in_reg - of type hwtLib.amba.axi_comp.buff.AxiBuff
- __init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: ~typing.Optional[str] = None)[source]¶
- gen_addr_logic(addr_ch_in: Axi4_addr, addr_ch_out: Axi4Lite_addr, req_fifo_inp: HandshakedIdAndLen)[source]¶
Instanciate logic which splits the transactions to a beats on AxiLite interface and propagate informations about the transacttions to req_fifo_inp for later use
- class hwtLib.amba.axi_comp.to_axiLite.HandshakedIdAndLen(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶
Bases:
HandshakeSync
- HDL params
ID_WIDTH - default value 4 of type int
LEN_WIDTH - default value 8 of type int
- HDL IO
id - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
len - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)
hwtLib.amba.axi_comp.virtualDma module¶
- class hwtLib.amba.axi_comp.virtualDma.AxiVirtualDma(axi: Union[Axi3, Axi3Lite, Axi4, Axi4Lite], alignas: int = 8, max_trans_overlap=16)[source]¶
Bases:
AbstractComponentBuilder
An object which can be used to generate read/write logic for AMBA AXI interfaces. It does these things:
Based on alignment of the data and data type it optimizes shift logic for alignment
If transaction can spawn over multiple AXI transactions it also generates the logic for dispatching and merging of such a transactions.
It propagates read/write/aligmnent and input errors as a hwt InHwExceptions
- Variables
alignas – specifies alignment requirement for a data type t (in bits), same functionailty as C++11 alignas specifier, used to discard alignment logic
- __init__(axi: Union[Axi3, Axi3Lite, Axi4, Axi4Lite], alignas: int = 8, max_trans_overlap=16)[source]¶
- Parameters
axi – AMBA AXI bus used to read the data
- build()[source]¶
Build an DMA logic from previously stacked reads/writes
- Note
placeholder for future use
- read(t: HdlType, tmpl: Optional[TransTmpl] = None, frames: Optional[List[FrameTmpl]] = None, transaction_id=0) Union[UnionSource, StructIntf, Handshaked] [source]¶
- Parameters
~.t – instance of HStruct which specifies data format to download
~.tmpl – instance of TransTmpl for this t
~.frames – list of FrameTmpl instances for this tmpl
~.transaction_id – id value for axi
- Note
if tmpl and frames are None they are resolved from structT parseTemplate
- Note
A single transaction can be split to multiple frames, if they are specified by “frames”.