hwtLib.amba.axi_comp package

Generic Axi3/4 componets

note

majority of componets can be also configured to use Axi3/4Lite interface instead

Submodules

hwtLib.amba.axi_comp.buff module

class hwtLib.amba.axi_comp.buff.AxiBuff(intfCls, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Transaction buffer for AXI3/4/Lite and others

HDL params
  • INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • ADDR_BUFF_DEPTH - default value 4 of type int

  • DATA_BUFF_DEPTH - default value 4 of type int

HDL IO
HDL components
schematic
__init__(intfCls, hdl_name_override: Optional[str] = None)[source]
hwtLib.amba.axi_comp.buff._example_AxiBuff()[source]

hwtLib.amba.axi_comp.buff_cdc module

class hwtLib.amba.axi_comp.buff_cdc.AxiBuffCdc(intfCls, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.amba.axi_comp.buff.AxiBuff

Clock domain crossing with buffers for AXI3/4/Lite and others

HDL params
  • INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • ADDR_BUFF_DEPTH - default value 5 of type int

  • DATA_BUFF_DEPTH - default value 5 of type int

  • M_FREQ - default value 102000000 of type int

  • S_FREQ - default value 102000000 of type int

HDL IO
HDL components
schematic
_setup_clk_rst_n()[source]
hwtLib.amba.axi_comp.buff_cdc._example_AxiBuffCdc()[source]

hwtLib.amba.axi_comp.builder module

class hwtLib.amba.axi_comp.builder.AxiBuilder(parent, srcInterface, name=None, master_to_slave=True)[source]

Bases: hwtLib.abstract.componentBuilder.AbstractComponentBuilder

Helper class wich simplifies instantiation and configuration of common components for Axi interfaces

BuffCdcCls

alias of hwtLib.amba.axi_comp.buff_cdc.AxiBuffCdc

BuffCls

alias of hwtLib.amba.axi_comp.buff.AxiBuff

_genericInstance(unit_cls, name, set_params=<function AxiBuilder.<lambda>>, update_params=True, propagate_clk_rst=True)[source]

Instantiate generic component and connect basics

Parameters
  • unit_cls – class of unit which is being created

  • name – name for unit_cls instance

  • set_params – function which updates parameters as is required (parameters are already shared with self.end interface)

buff(addr_items=1, data_items=1)[source]

Use registers and FIFOs to create buffer of specified paramters

Parameters

items – number of items in buffer

buff_cdc(clk, rst, addr_items=1, data_items=1)[source]

Instanciate a CDC (Clock Domain Crossing) buffer or AsyncFifo on selected interface

Note

if items==1 CDC clock synchronization register is used if items>1 asynchronous FIFO is used

resize(addr_width=None, data_width=None)[source]
to_avalon_mm(R_DATA_FIFO_DEPTH=16, R_SIZE_FIFO_DEPTH=16, RW_PRIORITY='READ')[source]
to_axi(axi_cls, id_width=0)[source]

hwtLib.amba.axi_comp.resize module

class hwtLib.amba.axi_comp.resize.AxiResize(intfCls, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Change DATA_WIDTH of axi interface

HDL params
  • INTF_CLS - default value <class ‘hwtLib.amba.axi4Lite.Axi4Lite’> of type type

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • OUT_DATA_WIDTH - default value 512 of type int

  • OUT_ADDR_WIDTH - default value 32 of type int

  • MAX_TRANS_OVERLAP - default value 4 of type int

HDL IO
HDL components
schematic
__init__(intfCls, hdl_name_override: Optional[str] = None)[source]
connect_shifted(src_ch, dst_ch, i)[source]
connect_with_padding(src, src_range, dst, dst_range)[source]
propagate_addr(m_a, s_a)[source]
select_data_word_from_ouput_word(m, s)[source]
hwtLib.amba.axi_comp.resize._example_AxiResize()[source]

hwtLib.amba.axi_comp.slave_timeout module

class hwtLib.amba.axi_comp.slave_timeout.AxiSlaveTimeout(intfCls, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

Component witch has internal timeout for r/b channel and responds with the error code if the slave does not respond in specified time

HDL params
  • TIMEOUT - default value 4096 of type int

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO
schematic
__init__(intfCls, hdl_name_override: Optional[str] = None)[source]
hwtLib.amba.axi_comp.slave_timeout._example_AxiSlaveTimeout()[source]

hwtLib.amba.axi_comp.static_remap module

class hwtLib.amba.axi_comp.static_remap.AxiStaticRemap(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.abstract.busStaticRemap.BusStaticRemap

BusStaticRemap implementation for AXI3/4 full/lite interfaces :note: this component only remaps some memory regions, but it does not perform the address checking

HDL params
  • INTF_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

  • MEM_MAP - default value [(0, 4096, 4096), (4096, 4096, 0)] of type list

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO
schematic
__init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: Optional[str] = None)[source]
hwtLib.amba.axi_comp.static_remap._example_AxiStaticRemap()[source]

hwtLib.amba.axi_comp.stream_to_mem module

class hwtLib.amba.axi_comp.stream_to_mem.Axi4streamToMem(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Most simple DMA for AXI4 interface.

  • 0x0 control reg.
    • bit 0, rw - on/off (1 means on)

    • bit 1, r - idle (1 if no transaction in progress)

0x4 baseAddr

Length of written data is specified by DATA_LEN. Input data is splited on smaller frames to fit MAX_BUTST_LEN.

If there is transaction pending idle flag is 0, if on/off is set to 0 in this state unit continues until all data are send and then stays off. This could be use as synchronization with the software.

  1. driver enables this unit, then tests while not idle.

  2. then waits while idle.

  3. then reads the data and back to 1

or unit is enabled and driver disables it only for the time of reading.

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • CNTRL_AW - default value 5 of type int

  • DATA_LEN - default value 33 of type int

  • MAX_BUTST_LEN - default value 16 of type int

HDL IO
HDL components
schematic
axiWAddrHandler(st, baseAddr, actualAddr, lenRem)[source]

AXI write addr logic

connectRegisters(st, onoff, baseAddr)[source]

connection of AXI-lite registers

dataWFeed(st, lenRem, actualLenRem)[source]

Connection between din and axi.w channel

mainFsm(st, onoff, lenRem, actualLenRem)[source]
w_allAck(st)[source]

In this clk data word will be transfered

hwtLib.amba.axi_comp.tester module

class hwtLib.amba.axi_comp.tester.AxiTester(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Tester for AXI3/4 interfaces

Can precisely control order and timing of read address/write address/read/write/write response transactions Allows to read and specify values of controls signals like cache/lock/burst etc…

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • CNTRL_DATA_WIDTH - default value 32 of type int

  • CNTRL_ADDR_WIDTH - default value 32 of type int

HDL IO
HDL components
schematic
__init__(axiCls=<class 'hwtLib.amba.axi4.Axi4'>, cntrlCls=<class 'hwtLib.amba.axi4Lite.Axi4Lite'>, hdl_name_override: Optional[str] = None)[source]
_add_ep()[source]

hwtLib.amba.axi_comp.to_axiLite module

class hwtLib.amba.axi_comp.to_axiLite.Axi_to_AxiLite(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.abstract.busBridge.BusBridge

AXI3/4 -> Axi4Lite bridge

Variables

MAX_TRANS_OVERLAP – depth of internal FIFO which is used to allow the transactions to overlap each other in order to pipeline the execution of transactions

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • MAX_TRANS_OVERLAP - default value 4 of type int

HDL IO
HDL components
schematic
__init__(intfCls=<class 'hwtLib.amba.axi4.Axi4'>, hdl_name_override: Optional[str] = None)[source]
gen_addr_logic(addr_ch_in: hwtLib.amba.axi4.Axi4_addr, addr_ch_out: hwtLib.amba.axi4Lite.Axi4Lite_addr, req_fifo_inp: hwtLib.amba.axi_comp.to_axiLite.HandshakedIdAndLen)[source]

Instanciate logic which splits the transactions to a beats on AxiLite interface and propagate informations about the transacttions to req_fifo_inp for later use

gen_b_or_r_logic(inp, outp, fifo_out, propagete_only_on_last)[source]

Use counter to skip intermediate generated transactions and pass only confirmation from last beat of the original transaction

gen_w_logic(w_in, w_out)[source]

Directly connect the w channels with ignore of extra signals (The data should be already synchronized by order of beats on channel)

class hwtLib.amba.axi_comp.to_axiLite.HandshakedIdAndLen(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.HandshakeSync

HDL params
  • ID_WIDTH - default value 4 of type int

  • LEN_WIDTH - default value 8 of type int

HDL IO

hwtLib.amba.axi_comp.virtualDma module

class hwtLib.amba.axi_comp.virtualDma.AxiVirtualDma(axi: Union[hwtLib.amba.axi3.Axi3, hwtLib.amba.axi3Lite.Axi3Lite, hwtLib.amba.axi4.Axi4, hwtLib.amba.axi4Lite.Axi4Lite], alignas: int = 8, max_trans_overlap=16)[source]

Bases: hwtLib.abstract.componentBuilder.AbstractComponentBuilder

An object which can be used to generate read/write logic for AMBA AXI interfaces. It does these things:

  • Based on alignment of the data and data type it optimizes shift logic for alignment

  • If transaction can spawn over multiple AXI transactions it also generates the logic for dispatching and merging of such a transactions.

  • It propagates read/write/aligmnent and input errors as a hwt InHwExceptions

Variables

alignas – specifies alignment requirement for a data type t (in bits), same functionailty as C++11 alignas specifier, used to discard alignment logic

__init__(axi: Union[hwtLib.amba.axi3.Axi3, hwtLib.amba.axi3Lite.Axi3Lite, hwtLib.amba.axi4.Axi4, hwtLib.amba.axi4Lite.Axi4Lite], alignas: int = 8, max_trans_overlap=16)[source]
Parameters

axi – AMBA AXI bus used to read the data

build()[source]

Build an DMA logic from previously stacked reads/writes

Note

placeholder for future use

read(t: hwt.hdl.types.hdlType.HdlType, tmpl: Optional[hwt.hdl.transTmpl.TransTmpl] = None, frames: Optional[List[hwt.hdl.frameTmpl.FrameTmpl]] = None, transaction_id=0) Union[hwt.interfaces.unionIntf.UnionSource, hwt.interfaces.structIntf.StructIntf, hwt.interfaces.std.Handshaked][source]
Parameters
  • t – instance of HStruct which specifies data format to download

  • tmpl – instance of TransTmpl for this t

  • frames – list of FrameTmpl instances for this tmpl

  • transaction_id – id value for axi

Note

if tmpl and frames are None they are resolved from structT parseTemplate

Note

A single transaction can be split to multiple frames, if they are specified by “frames”.

write(t: hwt.hdl.types.hdlType.HdlType, id_=0, tmpl: Optional[hwt.hdl.transTmpl.TransTmpl] = None, frames: Optional[List[hwt.hdl.frameTmpl.FrameTmpl]] = None)[source]

Rest of the paramters described in read()