hwtLib.amba.axis_comp package

This package is dedicated for a componets and utils which are related to AMBA AXI-stream (AXI4-Stream) interface

Subpackages

Submodules

hwtLib.amba.axis_comp.base module

class hwtLib.amba.axis_comp.base.Axi4SCompBase(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: HandshakedCompBase

Abstract base for axis components

__annotations__ = {}
__init__(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]
Parameters:

hshwIO – class of interface which should be used as interface of this unit

getDataWidthDependent(hwIO: Axi4Stream)[source]
classmethod get_ready_signal(hwIO: Axi4Stream)[source]
classmethod get_valid_signal(hwIO: Axi4Stream)[source]

hwtLib.amba.axis_comp.builder module

class hwtLib.amba.axis_comp.builder.Axi4SBuilder(parent: HwModule, srcInterface: HwIO | HObjList, name: str | None = None, master_to_slave: bool = True)[source]

Bases: AbstractStreamBuilder

Helper class which simplifies building of large stream paths

FifoAsyncCls

alias of Axi4SFifoAsync

FifoCls

alias of Axi4SFifo

FifoDropCls

alias of Axi4SFifoDrop

JoinPrioritizedCls

alias of Axi4SJoinPrioritized

RegCdcCls

alias of Axi4SCdc

RegCls

alias of Axi4SReg

ResizerCls

alias of Axi4S_resizer

SplitCopyCls

alias of Axi4SSplitCopy

SplitSelectCls

alias of Axi4SSpliSelect

__annotations__ = {}
buff_drop(items: int, export_size=False, export_space=False)[source]

Instantiate a FIFO buffer with externally controlled frame drop functionality (use “dataIn_discard” signal)

classmethod constant_frame(parent: HwModule, value: bytes | Tuple[int | HBitsConst | None, ...], data_width: int, use_strb: bool = False, use_keep: bool = False, repeat=True, name=None) → Axi4SBuilder[source]

Instantiate a constant buffer which wil produce the frame of specified data

classmethod deparse(parent: HwModule, typeToForge: HdlType, hwIO: Axi4Stream, setupFn=None, name: str = None) → Tuple[Axi4SBuilder, HwIOStruct][source]

generate frame assembler for specified type :note: you can set endianity and others in setupFn

Parameters:

  • parent – HwModule where generated units should be instantiated

  • typeToForge – instance of HType used as template for frame to assembly

  • hwIO – class for output interface

  • setupFn – setup function for output interface

  • name – name prefix for generated units

Returns:

tuple (builder, interface with deparsed frame)

parse(typeToParse) → HwIOStruct[source]
Parameters:

typeToParse – structuralized type to parse

Returns:

interface with parsed data (e.g. HwIOStruct for HStruct)

resize(newDataWidth)[source]

Change data width of axi stream

startOfFrame() → RtlSignal[source]

generate start of frame signal, high when we expect new frame to start

to_avalonSt() → AvalonSTBuilder[source]

hwtLib.amba.axis_comp.cdc module

class hwtLib.amba.axis_comp.cdc.Axi4SCdc(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedCdc

CDC (Clock domain crossing) for axi-stream like interfaces

HDL params:

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • DATA_RESET_VAL - default value None of type None

  • IN_FREQ - default value 100000000 of type int

  • OUT_FREQ - default value 100000000 of type int

HDL IO:

  • dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

HDL components:
schematic
__annotations__ = {}
hwtLib.amba.axis_comp.cdc.example_Axi4SCdc()[source]

hwtLib.amba.axis_comp.en module

class hwtLib.amba.axis_comp.en.Axi4S_en(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase

This component is like on-off switch for axi stream interface which does care about frames. If en signal is 0 current frame is finished and next frame is started only when en is 1

HDL params:

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

schematic
__annotations__ = {}

hwtLib.amba.axis_comp.fifo module

class hwtLib.amba.axis_comp.fifo.Axi4SFifo(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedFifo

Synchronous fifo for axi-stream interface.

HDL params:

  • DEPTH - default value 4 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:
HDL components:
schematic
__annotations__ = {}
hwtLib.amba.axis_comp.fifo._example_Axi4SFifo()[source]

hwtLib.amba.axis_comp.fifoCopy module

class hwtLib.amba.axis_comp.fifoCopy.Axi4SFifoCopy(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedFifo

Synchronous FIFO for axi-stream interface which can copy last frame or work as a regular FIFO.

HDL params:

  • DEPTH - default value 4 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 2 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

  • dataOut_copy_frame - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • dataOut_replacement_id - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

HDL components:
schematic
FIFO_CLS

alias of FifoCopy

REG_CLS

alias of NotImplementedError

__annotations__ = {}
_connect_fifo_in()[source]
_connect_fifo_out(out_clk, out_rst)[source]
_declr_io()[source]
class hwtLib.amba.axis_comp.fifoCopy.Axi4SRegCopy(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedFifo

Same thing as a Axi4SFifoCopy just uses registers without fifo pointers

HDL params:

  • DEPTH - default value 0 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

  • dataOut_copy_frame - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

HDL components:
schematic
REG_CLS

alias of NotImplementedError

__annotations__ = {}
hwtLib.amba.axis_comp.fifoCopy._example_Axi4SFifoCopy()[source]

hwtLib.amba.axis_comp.fifoDrop module

class hwtLib.amba.axis_comp.fifoDrop.Axi4SFifoDrop(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedFifoDrop

Synchronous FIFO for axi-stream interface with frame drop functionality and speculative buffering. Also known as a speculative FIFO.

HDL params:

  • DEPTH - default value 4 of type int

  • EXPORT_SIZE - default value True of type bool

  • EXPORT_SPACE - default value True of type bool

  • INIT_DATA - default value () of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

  • size - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits, unsigned> - MASTER

  • space - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits, unsigned> - MASTER

  • dataIn_discard - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

HDL components:
schematic
REG_CLS

alias of NotImplementedError

__annotations__ = {}
_connect_fifo_in()[source]
hwtLib.amba.axis_comp.fifoDrop._example_Axi4SFifoDrop()[source]

hwtLib.amba.axis_comp.fifoFrameReversing module

class hwtLib.amba.axis_comp.fifoFrameReversing.Axi4S_fifoFrameReversing(hdlName: str | None = None)[source]

Bases: HwModule

FIFO which returns the word of the frame in reversal order

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value True of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • MAX_PKT_WORDS - default value 255 of type intmax number of words per packet

  • MAX_PKT_CNT - default value 2 of type intmax number of packets in storable in this FIFO

  • DEPTH - default value 510 of type intmax number of packet words storable in this FIFO

  • INIT_DATA - default value () of type tuple

HDL IO:
HDL components:
schematic
REG_CLS

alias of NotImplementedError

__annotations__ = {}
class hwtLib.amba.axis_comp.fifoFrameReversing.HwIoFifoIndexTuple(masterDir=DIRECTION.OUT, hdlName: str | dict[str, str] | None = None, loadConfig=True)[source]

Bases: HwIORdVldSync

__annotations__ = {}
hwtLib.amba.axis_comp.fifoFrameReversing._example_Axi4S_fifoFrameReversing()[source]

hwtLib.amba.axis_comp.fifoMeasuring module

class hwtLib.amba.axis_comp.fifoMeasuring.Axi4S_fifoMeasuring(hdlName: str | None = None)[source]

Bases: HwModule

FIFO which are counting sizes of frames and sends it over dedicated handshaked interface “sizes”

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value True of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • SIZES_BUFF_DEPTH - default value 4 of type int

  • MAX_LEN - default value 15 of type int

  • EXPORT_ALIGNMENT_ERROR - default value False of type bool

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

  • sizes - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

HDL components:
schematic
REG_CLS

alias of NotImplementedError

__annotations__ = {}
getAlignBitsCnt()[source]
hwtLib.amba.axis_comp.fifoMeasuring._example_Axi4S_fifoMeasuring()[source]

hwtLib.amba.axis_comp.fifo_async module

class hwtLib.amba.axis_comp.fifo_async.Axi4SFifoAsync(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HsFifoAsync

Asnchronous fifo for axi-stream interface.

HDL params:

  • DEPTH - default value 5 of type int

  • EXPORT_SIZE - default value False of type bool

  • EXPORT_SPACE - default value False of type bool

  • INIT_DATA - default value () of type tuple

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • IN_FREQ - default value 100000000 of type int

  • OUT_FREQ - default value 100000000 of type int

HDL IO:

  • dataIn_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataOut_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • dataIn_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

HDL components:
schematic
__annotations__ = {}
hwtLib.amba.axis_comp.fifo_async._example_Axi4SFifoAsync()[source]

hwtLib.amba.axis_comp.frameGen module

class hwtLib.amba.axis_comp.frameGen.Axi4sFrameGen(hdlName: str | None = None)[source]

Bases: HwModule

Generator of AXI stream frames for testing purposes

HDL params:

  • MAX_LEN - default value 511 of type int

  • CNTRL_ADDR_WIDTH - default value 4 of type int

  • CNTRL_DATA_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • USE_STRB - default value True of type bool

HDL IO:
HDL components:
schematic
__annotations__ = {}

hwtLib.amba.axis_comp.joinPrioritized module

class hwtLib.amba.axis_comp.joinPrioritized.Axi4SJoinPrioritized(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HsJoinPrioritized

Join input stream to single output stream inputs with lower number has higher priority

HDL params:

  • INPUTS - default value 2 of type int

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataIn - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

HDL components:
schematic
__annotations__ = {}

hwtLib.amba.axis_comp.reg module

class hwtLib.amba.axis_comp.reg.Axi4SReg(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HandshakedReg

Register for Axi4Stream interfaces

HDL params:

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • LATENCY - default value 1 of type int

  • DELAY - default value 0 of type int

  • INIT_DATA - default value () of type tuple

HDL IO:
schematic
__annotations__ = {}
hwtLib.amba.axis_comp.reg._example_Axi4SReg()[source]

hwtLib.amba.axis_comp.resizer module

class hwtLib.amba.axis_comp.resizer.Axi4S_resizer(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase

Change data with of Axi4Stream interface

Attention:

start of frame is expected to be aligned on first word

Attention:

strb can be not fully set only in last word

Attention:

in upscale mode id and other signals which are not dependent on data width are propagated only from last word

Note:

interface is configurable and schematic is example with Axi4Stream

Note:

first schematic is for upsize mode, second one is for downsize mode

schematicschematic
__annotations__ = {}
downscale(IN_DW, OUT_DW)[source]
nextAreNotValidLogic(inStrb, actualItemIndx, ITEMS, ITEM_DW)[source]
upscale(IN_DW, OUT_DW)[source]
hwtLib.amba.axis_comp.resizer._example_Axi4S_resizer_downscale()[source]
hwtLib.amba.axis_comp.resizer._example_Axi4S_resizer_upscale()[source]

hwtLib.amba.axis_comp.splitCopy module

class hwtLib.amba.axis_comp.splitCopy.Axi4SSplitCopy(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HsSplitCopy

Stream duplicator for Axi4Stream interfaces

HDL params:

  • OUTPUTS - default value 2 of type int

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:
schematic
__annotations__ = {}

hwtLib.amba.axis_comp.splitSelect module

class hwtLib.amba.axis_comp.splitSelect.Axi4SSpliSelect(hwIOCls=<class 'hwtLib.amba.axi4s.Axi4Stream'>, hdlName: str | None = None)[source]

Bases: Axi4SCompBase, HsSplitSelect

Send input frame to one of N output streams as specified by selectOneHot interface

HDL params:

  • OUTPUTS - default value 3 of type int

  • HWIO_CLS - default value <class ‘hwtLib.amba.axi4s.Axi4Stream’> of type type

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • selectOneHot - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

  • dataIn - of type hwtLib.amba.axi4s.Axi4Stream - SLAVE

  • dataOut - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

HDL components:
schematic
__annotations__ = {}
_select_consume_en()[source]

hwtLib.amba.axis_comp.storedBurst module

class hwtLib.amba.axis_comp.storedBurst.Axi4SStoredBurst(hdlName: str | None = None)[source]

Bases: HwModule

This unit send data stored in property DATA over axi-stream interface

Variables:

  • ~.DATA – bytes or integer values for each word

  • ~.REPEAT – if False this component works in one-shot mode

HDL params:

  • IS_BIGENDIAN - default value False of type bool

  • USE_STRB - default value False of type bool

  • USE_KEEP - default value False of type bool

  • ID_WIDTH - default value 0 of type int

  • DEST_WIDTH - default value 0 of type int

  • DATA_WIDTH - default value 64 of type int

  • USER_WIDTH - default value 0 of type int

  • REPEAT - default value False of type bool

  • DATA - default value b’Hello world!!!!!’ of type bytes

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • dataOut - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

schematic
__annotations__ = {}
dataRd()[source]
nextWordIndexLogic(wordIndex: RtlSignal, DATA_LEN: int)[source]

hwtLib.amba.axis_comp.strformat module

class hwtLib.amba.axis_comp.strformat.Axi4S_strFormat(hdlName: str | None = None)[source]

Bases: HwModule

Generate component which does same thing as printf just in hw. The output string is stream of encoded characters. The ending ‘0’ is not appended. And ‘last’ signal of Axi4Stream is used instead.

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • FORMAT - default value (‘Axi4S_strFormat: hex: 0x’, <Axi4S_strFormatItem (‘data’,), x, 8>, ‘, dec: ‘, <Axi4S_strFormatItem (‘data’,), d, 10>, ‘ is the value of data from example’) of type tuple

  • INPUT_T - default value struct { <HBits, 32bits, unsigned> data } of type hwt.hdl.types.struct.HStruct

  • ENCODING - default value utf-8 of type str

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • data_in - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 32bits, unsigned> data } - SLAVE

  • data_out - of type hwtLib.amba.axi4s.Axi4Stream - MASTER

HDL components:
schematic
__annotations__ = {}
build_string_rom()[source]

Collect all const strings and char translation tables and pack them in to a content of string rom

connect_single_format_group(f_i: int, f: str | Axi4S_strFormatItem, strings_offset_and_size: Dict[int | str, Tuple[int, int]], string_rom: RtlSignal, char_i: RtlSignal, to_bcd_inputs: List[Tuple[RtlSignal, HdlStatement]], en: RtlSignal)[source]

Connect a single formating group or string chunk to output. Depending on item type this may involve:

  • iterate the string characters stored in string_rom

  • iterate and translate bin/oct/hex characters

  • register bcd input for later connection

  • connect an input string from an input Axi4Stream

create_char_mux(in_, out_, char_i, digits, bits_per_digit)[source]

Create a MUX which select the degit from input vector. Also perform necessary type casting for corner cases.

class hwtLib.amba.axis_comp.strformat.Axi4S_strFormatItem(member_path: TypePath, format_type: str, digits: int)[source]

Bases: object

Variables:

  • member_path – path which specifies the location of interface with the value on input interface

  • digits – number of digitsof output formated number (not used for ‘s’ format)

  • format_type – is one of following characters. +——+——————————-+ | char | format meaning | +======+===============================+ | ‘d’ | decadic number | +——+——————————-+ | ‘b’ | binary number | +——+——————————-+ | ‘o’ | octal number | +——+——————————-+ | ‘x’ | hexadecimal number lowercase | +——+——————————-+ | ‘X’ | hexadecimal number uppercase | +——+——————————-+ | ‘s’ | string | +——+——————————-+

  • leading_char_fill (str) – character which should be used to fill leading digits if number of digits is used but the value have less digits

BITS_PER_CHAR = {'X': 4, 'b': 1, 'd': 4, 'o': 3, 'x': 4}
__init__(member_path: TypePath, format_type: str, digits: int)[source]
__repr__()[source]

Return repr(self).

class hwtLib.amba.axis_comp.strformat.HdlType_to_Interface_with_Axi4Stream[source]

Bases: HdlType_to_HwIO

apply(dtype: HdlType, field_path: TypePath | None = None) → HwIO[source]

Run the conversion

hwtLib.amba.axis_comp.strformat_fn module

hwtLib.amba.axis_comp.strformat_fn._parse_format_groups(f_str: str) → Generator[str | Axi4S_strFormatItem, None, None][source]
hwtLib.amba.axis_comp.strformat_fn.axiS_strFormat(parent: HwModule, name: str, data_width: int, format_str: str, *args, **kwargs)[source]

Instantiate an hwtLib.amba.axis_comp.strformat.Axi4S_strFormat using simplified str.format syntax The syntax is allows for an utf-8 string with a variable format groups and several escape sequences in addition to normal string escape sequences.

The escape sequences are (same as str.format())

+=======+=================+
| char  | escape sequence |
+=======+=================+
| {     | {{              |
+-------+-----------------+
| }     | }}              |
+-------+-----------------+

The syntax for format group is as folowing:

{[index/name]:[nuber_of_digits][type]}