hwtLib.amba.axis_comp package

This package is dedicated for a componets and utils which are related to AMBA AXI-stream (AXI4-Stream) interface

Subpackages

• hwtLib.amba.axis_comp.frame_deparser package
  • Submodules
  • hwtLib.amba.axis_comp.frame_deparser.strb_keep_stash module
  • hwtLib.amba.axis_comp.frame_deparser.test_types module
  • hwtLib.amba.axis_comp.frame_deparser.utils module
• hwtLib.amba.axis_comp.frame_join package
  • Submodules
  • hwtLib.amba.axis_comp.frame_join.input_reg module
• hwtLib.amba.axis_comp.frame_parser package
  • Submodules
  • hwtLib.amba.axis_comp.frame_parser.field_connector module
  • hwtLib.amba.axis_comp.frame_parser.footer_split module
  • hwtLib.amba.axis_comp.frame_parser.out_containers module
  • hwtLib.amba.axis_comp.frame_parser.test_types module
  • hwtLib.amba.axis_comp.frame_parser.word_factory module

Submodules

hwtLib.amba.axis_comp.base module

class hwtLib.amba.axis_comp.base.AxiSCompBase(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: HandshakedCompBase

Abstract base for axis components

__init__(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Parameters

hsIntfCls – class of interface which should be used as interface of this unit

getDataWidthDependent(intf)

classmethod get_ready_signal(intf)

classmethod get_valid_signal(intf)

hwtLib.amba.axis_comp.builder module

class hwtLib.amba.axis_comp.builder.AxiSBuilder(parent: Unit, srcInterface: Union[Interface, HObjList], name: Optional[str] = None, master_to_slave: bool = True)

Bases: AbstractStreamBuilder

Helper class which simplifies building of large stream paths

FifoAsyncCls

alias of AxiSFifoAsync

FifoCls

alias of AxiSFifo

FifoDropCls

alias of AxiSFifoDrop

JoinPrioritizedCls

alias of AxiSJoinPrioritized

RegCdcCls

alias of AxiSCdc

RegCls

alias of AxiSReg

ResizerCls

alias of AxiS_resizer

SplitCopyCls

alias of AxiSSplitCopy

SplitSelectCls

alias of AxiSSpliSelect

buff_drop(items: int, export_size=False, export_space=False)

Instantiate a FIFO buffer with externally controlled frame drop functionality (use “dataIn_discard” signal)

classmethod constant_frame(parent: Unit, value: Union[bytes, Tuple[Optional[Union[int, BitsVal]], ...]], data_width: int, use_strb: bool = False, use_keep: bool = False, repeat=True, name=None) → AxiSBuilder

Instantiate a constant buffer which wil produce the frame of specified data

classmethod deparse(parent: Unit, typeToForge: HdlType, intfCls: AxiStream, setupFn=None, name: Optional[str] = None) → Tuple[AxiSBuilder, StructIntf]

generate frame assembler for specified type :note: you can set endianity and others in setupFn

Parameters

• parent – unit where generated units should be instantiated

• typeToForge – instance of HType used as template for frame to assembly

• intfCls – class for output interface

• setupFn – setup function for output interface

• name – name prefix for generated units

Returns

tuple (builder, interface with deparsed frame)

parse(typeToParse) → StructIntf

Parameters

typeToParse – structuralized type to parse

Returns

interface with parsed data (e.g. StructIntf for HStruct)

resize(newDataWidth)

Change data width of axi stream

startOfFrame() → RtlSignal

generate start of frame signal, high when we expect new frame to start

hwtLib.amba.axis_comp.cdc module

class hwtLib.amba.axis_comp.cdc.AxiSCdc(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedCdc

CDC (Clock domain crossing) for axi-stream like interfaces

HDL params

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

• DATA_RESET_VAL - default value None of type None

• IN_FREQ - default value 100000000 of type int

• OUT_FREQ - default value 100000000 of type int

HDL IO

• dataIn_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• dataIn_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataOut_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• dataOut_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• in_ack_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen

• out_en_pulse_gen - of type hwtLib.clocking.cdc.CdcPulseGen

• tx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM

• rx_fsm - of type hwtLib.handshaked.cdc.HandshakeFSM

schematic

hwtLib.amba.axis_comp.cdc.example_AxiSCdc()

hwtLib.amba.axis_comp.en module

class hwtLib.amba.axis_comp.en.AxiS_en(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase

This component is like on-off switch for axi stream interface which does care about frames. If en signal is 0 current frame is finished and next frame is started only when en is 1

HDL params

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• en - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

schematic

hwtLib.amba.axis_comp.fifo module

class hwtLib.amba.axis_comp.fifo.AxiSFifo(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedFifo

Synchronous fifo for axi-stream interface.

HDL params

• DEPTH - default value 4 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• fifo - of type hwtLib.mem.fifo.Fifo

schematic

hwtLib.amba.axis_comp.fifo._example_AxiSFifo()

hwtLib.amba.axis_comp.fifoCopy module

class hwtLib.amba.axis_comp.fifoCopy.AxiSFifoCopy(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedFifo

Synchronous fifo for axi-stream interface which can copy last frame or work as a regular fifo.

HDL params

• DEPTH - default value 4 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 2 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

• dataOut_copy_frame - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• dataOut_replacement_id - of type hwt.interfaces.std.Signal with dtype=<Bits, 2bits> - SLAVE

HDL components

• fifo - of type hwtLib.mem.fifoCopy.FifoCopy

schematic

FIFO_CLS

alias of FifoCopy

_connect_fifo_in()

_connect_fifo_out(out_clk, out_rst)

_declr_io()

class hwtLib.amba.axis_comp.fifoCopy.AxiSRegCopy(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedFifo

Same thing as a AxiSFifoCopy just uses registers without fifo pointers

HDL params

• DEPTH - default value 0 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

• dataOut_copy_frame - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

HDL components

• reg - of type hwtLib.amba.axis_comp.reg.AxiSReg

schematic

hwtLib.amba.axis_comp.fifoCopy._example_AxiSFifoCopy()

hwtLib.amba.axis_comp.fifoDrop module

class hwtLib.amba.axis_comp.fifoDrop.AxiSFifoDrop(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedFifoDrop

Synchronous fifo for axi-stream interface with frame drop functionality and speculative buffering. Also known as a speculative fifo.

HDL params

• DEPTH - default value 4 of type int

• EXPORT_SIZE - default value True of type bool

• EXPORT_SPACE - default value True of type bool

• INIT_DATA - default value () of type tuple

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

• size - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits, unsigned> - MASTER

• space - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits, unsigned> - MASTER

• dataIn_discard - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

HDL components

• fifo - of type hwtLib.mem.fifoDrop.FifoDrop

schematic

_connect_fifo_in()

hwtLib.amba.axis_comp.fifoDrop._example_AxiSFifoDrop()

hwtLib.amba.axis_comp.fifoMeasuring module

class hwtLib.amba.axis_comp.fifoMeasuring.AxiS_fifoMeasuring(hdl_name_override: Optional[str] = None)

Bases: Unit

Fifo which are counting sizes of frames and sends it over dedicated handshaked interface “sizes”

HDL params

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value True of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

• SIZES_BUFF_DEPTH - default value 4 of type int

• MAX_LEN - default value 15 of type int

• EXPORT_ALIGNMENT_ERROR - default value False of type bool

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

• sizes - of type hwt.interfaces.std.Handshaked - MASTER

HDL components

• dataBuff - of type hwtLib.amba.axis_comp.fifo.AxiSFifo

• sizesBuff - of type hwtLib.handshaked.fifo.HandshakedFifo

• gen_dataIn_reg_0 - of type hwtLib.amba.axis_comp.reg.AxiSReg

schematic

getAlignBitsCnt()

hwtLib.amba.axis_comp.fifoMeasuring._example_AxiS_fifoMeasuring()

hwtLib.amba.axis_comp.fifo_async module

class hwtLib.amba.axis_comp.fifo_async.AxiSFifoAsync(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HsFifoAsync

Asnchronous fifo for axi-stream interface.

HDL params

• DEPTH - default value 5 of type int

• EXPORT_SIZE - default value False of type bool

• EXPORT_SPACE - default value False of type bool

• INIT_DATA - default value () of type tuple

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

• IN_FREQ - default value 100000000 of type int

• OUT_FREQ - default value 100000000 of type int

HDL IO

• dataIn_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• dataOut_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• dataIn_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• fifo - of type hwtLib.mem.fifoAsync.FifoAsync

schematic

hwtLib.amba.axis_comp.fifo_async._example_AxiSFifoAsync()

hwtLib.amba.axis_comp.frameGen module

class hwtLib.amba.axis_comp.frameGen.AxisFrameGen(hdl_name_override: Optional[str] = None)

Bases: Unit

Generator of axi stream frames for testing purposes

HDL params

• MAX_LEN - default value 511 of type int

• CNTRL_ADDR_WIDTH - default value 4 of type int

• CNTRL_DATA_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

• USE_STRB - default value True of type bool

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• axis_out - of type hwtLib.amba.axis.AxiStream - MASTER

• cntrl - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

HDL components

• conv - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

hwtLib.amba.axis_comp.joinPrioritized module

class hwtLib.amba.axis_comp.joinPrioritized.AxiSJoinPrioritized(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HsJoinPrioritized

Join input stream to single output stream inputs with lower number has higher priority

HDL params

• INPUTS - default value 2 of type int

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn_0 - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataIn_1 - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• join - of type hwtLib.handshaked.joinPrioritized.HsJoinPrioritized

schematic

hwtLib.amba.axis_comp.reg module

class hwtLib.amba.axis_comp.reg.AxiSReg(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HandshakedReg

Register for AxiStream interfaces

HDL params

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

• LATENCY - default value 1 of type int

• DELAY - default value 0 of type int

• INIT_DATA - default value () of type tuple

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

schematic

hwtLib.amba.axis_comp.reg._example_AxiSReg()

hwtLib.amba.axis_comp.resizer module

class hwtLib.amba.axis_comp.resizer.AxiS_resizer(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase

Change data with of AxiStream interface

Attention

start of frame is expected to be aligned on first word

Attention

strb can be not fully set only in last word

Attention

in upscale mode id and other signals which are not dependent on data width are propagated only from last word

Note

interface is configurable and schematic is example with AxiStream

Note

first schematic is for upsize mode, second one is for downsize mode

schematicschematic

downscale(IN_DW, OUT_DW)

nextAreNotValidLogic(inStrb, actualItemIndx, ITEMS, ITEM_DW)

upscale(IN_DW, OUT_DW)

hwtLib.amba.axis_comp.resizer._example_AxiS_resizer_downscale()

hwtLib.amba.axis_comp.resizer._example_AxiS_resizer_upscale()

hwtLib.amba.axis_comp.splitCopy module

class hwtLib.amba.axis_comp.splitCopy.AxiSSplitCopy(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HsSplitCopy

Stream duplicator for AxiStream interfaces

HDL params

• OUTPUTS - default value 2 of type int

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut_0 - of type hwtLib.amba.axis.AxiStream - MASTER

• dataOut_1 - of type hwtLib.amba.axis.AxiStream - MASTER

schematic

hwtLib.amba.axis_comp.splitSelect module

class hwtLib.amba.axis_comp.splitSelect.AxiSSpliSelect(intfCls=<class 'hwtLib.amba.axis.AxiStream'>, hdl_name_override: ~typing.Optional[str] = None)

Bases: AxiSCompBase, HsSplitSelect

Send input frame to one of N output streams as specified by selectOneHot interface

HDL params

• OUTPUTS - default value 3 of type int

• INTF_CLS - default value <class ‘hwtLib.amba.axis.AxiStream’> of type type

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• selectOneHot - of type hwt.interfaces.std.Handshaked - SLAVE

• dataIn - of type hwtLib.amba.axis.AxiStream - SLAVE

• dataOut_0 - of type hwtLib.amba.axis.AxiStream - MASTER

• dataOut_1 - of type hwtLib.amba.axis.AxiStream - MASTER

• dataOut_2 - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• selReg - of type hwtLib.handshaked.reg.HandshakedReg

schematic

_select_consume_en()

hwtLib.amba.axis_comp.storedBurst module

class hwtLib.amba.axis_comp.storedBurst.AxiSStoredBurst(hdl_name_override: Optional[str] = None)

Bases: Unit

This unit send data stored in property DATA over axi-stream interface

Variables

• ~.DATA – bytes or integer values for each word

• ~.REPEAT – if False this component works in one-shot mode

HDL params

• IS_BIGENDIAN - default value False of type bool

• USE_STRB - default value False of type bool

• USE_KEEP - default value False of type bool

• ID_WIDTH - default value 0 of type int

• DEST_WIDTH - default value 0 of type int

• DATA_WIDTH - default value 64 of type int

• USER_WIDTH - default value 0 of type int

• REPEAT - default value False of type bool

• DATA - default value b’Hello world!!!!!’ of type bytes

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• dataOut - of type hwtLib.amba.axis.AxiStream - MASTER

schematic

dataRd()

nextWordIndexLogic(wordIndex: RtlSignal, DATA_LEN: int)

hwtLib.amba.axis_comp.strformat module

class hwtLib.amba.axis_comp.strformat.AxiS_strFormat(hdl_name_override: Optional[str] = None)

Bases: Unit

Generate compomonent which does same thing as printf just in hw. The output string is stream of encoded characters. The ending ‘0’ is not appended. And ‘last’ signal of AxiStream is used instead.

HDL params

• DATA_WIDTH - default value 8 of type int

• FORMAT - default value (‘AxiS_strFormat: hex: 0x’, <AxiS_strFormatItem (‘data’,), x, 8>, ‘, dec: ‘, <AxiS_strFormatItem (‘data’,), d, 10>, ‘ is the value of data from example’) of type tuple

• INPUT_T - default value struct { <Bits, 32bits, unsigned> data } of type hwt.hdl.types.struct.HStruct

• ENCODING - default value utf-8 of type str

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• data_in - of type hwt.interfaces.structIntf.StructIntf with dtype=struct { <Bits, 32bits, unsigned> data } - SLAVE

• data_out - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• bin_to_bcd - of type hwtLib.logic.binToBcd.BinToBcd

schematic

build_string_rom()

Collect all const strings and char translation tables and pack them in to a content of string rom

connect_single_format_group(f_i: int, f: Union[str, AxiS_strFormatItem], strings_offset_and_size: Dict[Union[int, str], Tuple[int, int]], string_rom: RtlSignal, char_i: RtlSignal, to_bcd_inputs: List[Tuple[RtlSignal, HdlStatement]], en: RtlSignal)

Connect a single formating group or string chunk to output. Depending on item type this may involve:

• iterate the string characters stored in string_rom

• iterate and translate bin/oct/hex characters

• register bcd input for later connection

• connect an input string from an input AxiStream

create_char_mux(in_, out_, char_i, digits, bits_per_digit)

Create a MUX which select the degit from input vector. Also perform necessary type casting for corner cases.

class hwtLib.amba.axis_comp.strformat.AxiS_strFormatItem(member_path: TypePath, format_type: str, digits: int)

Bases: object

Variables

• member_path – path which specifies the loacation of interface with the value on input interface

• digits – number of digitsof output formated number (not used for ‘s’ format)

• format_type – is one of folloving characters. +——+——————————-+ | char | format meaning | +======+===============================+ | ‘d’ | decadic number | +——+——————————-+ | ‘b’ | binary number | +——+——————————-+ | ‘o’ | octal number | +——+——————————-+ | ‘x’ | hexadecimal number lowercase | +——+——————————-+ | ‘X’ | hexadecimal number uppercase | +——+——————————-+ | ‘s’ | string | +——+——————————-+

• leading_char_fill (str) – character which should be used to fill leading digits if number of digits is used but the value have less digits

BITS_PER_CHAR = {'X': 4, 'b': 1, 'd': 4, 'o': 3, 'x': 4}

__init__(member_path: TypePath, format_type: str, digits: int)

__repr__()

Return repr(self).

class hwtLib.amba.axis_comp.strformat.HdlType_to_Interface_with_AxiStream

Bases: HdlType_to_Interface

apply(dtype: HdlType, field_path: Optional[TypePath] = None) → Interface

Run the connversion

hwtLib.amba.axis_comp.strformat_fn module

hwtLib.amba.axis_comp.strformat_fn._parse_format_groups(f_str: str) → Generator[Union[str, AxiS_strFormatItem], None, None]

hwtLib.amba.axis_comp.strformat_fn.axiS_strFormat(parent: Unit, name: str, data_width: int, format_str: str, *args, **kwargs)

Instanciate an hwtLib.amba.axis_comp.strformat.AxiS_strFormat using simplified str.format syntax The syntax is allows for an utf-8 string with a variable format groups and several escape sequences in addition to normal string escape sequences.

The escape sequences are (same as str.format())

+=======+=================+
| char  | escape sequence |
+=======+=================+
| {     | {{              |
+-------+-----------------+
| }     | }}              |
+-------+-----------------+

The syntax for format group is as folowing:

{[index/name]:[nuber_of_digits][type]}

• The index or name specifies the name or the index of the input parameter.

• The width specifies how mahy digits should the output have.

• Format types can be found at hwtLib.amba.axis_comp.strformat.AxiS_strFormatItem

• If nuber_of_digits starts with 0 the leading zeros will be used instead of default space char (‘ ‘)

• The sign char is included in nuber_of_digits (‘{0:04X}’.format(-1) == ‘-001’)

• The type is described in hwtLib.amba.axis_comp.strformat.AxiS_strFormatItem