hwtLib.amba.datapump package¶

This package contains a AxiDatapump interfaces and components for them

note: AxiDatapump interface is simplified AXI-3/4 interface

Subpackages¶

hwtLib.amba.datapump.interconnect package

Submodules¶

hwtLib.amba.datapump.base module¶

class hwtLib.amba.datapump.base.AxiDatapumpBase(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶

Bases: Unit

Variables

~.MAX_TRANS_OVERLAP – max number of concurrent transactions
~.CHUNK_WIDTH – number of bits for one transaction chunk (a transaction is defined as a stream of chunks, if CHUNK_WIDTH==DATA_WIDTH it means that the transaction size % DATA_WIDTH == 0)
~.MAX_CHUNKS – maximum number of chunks in a transaction
~.ALIGNAS – specifies alignment requirement for a data type t (in bits), same functionailty as C++11 alignas specifier, used to discard alignment logic
~.driver – interface which is used to drive this datapump (AxiRDatapumpIntf or AxiWDatapumpIntf)

__init__(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶

addrAlign(addr: RtlSignal)[source]¶

addrHandler(req: AddrSizeHs, axiA: Union[Axi3_addr, Axi3Lite_addr, Axi4_addr, Axi4Lite_addr], transInfo: HandshakeSync, errFlag: RtlSignal)[source]¶: Propagate read/write requests from req to axi address channel and store extra info using transInfo interface.

addrIsAligned(addr: RtlSignal)[source]¶

axiAddrDefaults(a: Union[Axi3_addr, Axi3Lite_addr, Axi4_addr, Axi4Lite_addr])[source]¶

encodeShiftValue(SHIFT_OPTIONS: List[int], addrOffset: RtlSignal, shift: RtlSignal)[source]¶

getAxiLenMax()[source]¶

getBurstAddrOffset()[source]¶

getLen_t()[source]¶

getShiftOptions()[source]¶

getSizeAlignBits()[source]¶

hasAlignmentError(addr: RtlSignal)[source]¶

isAlwaysAligned()[source]¶

isCrossingWordBoundary(addr, rem)[source]¶

useTransSplitting()[source]¶

hwtLib.amba.datapump.intf module¶

class hwtLib.amba.datapump.intf.AddrSizeHs(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

HDL params

ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_LEN - default value 511 of type intmaximum value of len (number of words - 1)
USE_STRB - default value True of type bool

HDL IO

id - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER
addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 32bits> - MASTER
len - of type hwt.interfaces.std.Signal with dtype=<Bits, 9bits> - MASTER
rem - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.amba.datapump.intf.AddrSizeHsAgent(sim: HdlSimulator, intf: Handshaked, allowNoReset=False)[source]¶

Bases: HandshakedAgent

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwtLib.amba.datapump.intf.AxiRDatapumpIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Interface

Interface of read datapump driver

HDL params

ID_WIDTH - default value 0 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_BYTES - default value 4096 of type int
USE_STRB - default value True of type bool

HDL IO

req - of type hwtLib.amba.datapump.intf.AddrSizeHs - MASTER
r - of type hwtLib.amba.axis.AxiStream - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.amba.datapump.intf.AxiRDatapumpIntfAgent(sim: HdlSimulator, intf)[source]¶

Bases: AgentBase

Composite agent with agent for every AxiRDatapumpIntf channel enable is shared

__init__(sim: HdlSimulator, intf)[source]¶

property enable¶

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

class hwtLib.amba.datapump.intf.AxiWDatapumpIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Interface

Interface of write datapump driver

HDL params

ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_LEN - default value 511 of type int
USE_STRB - default value True of type bool

HDL IO

req - of type hwtLib.amba.datapump.intf.AddrSizeHs - MASTER
w - of type hwtLib.amba.axis.AxiStream - MASTER
ack - of type hwt.interfaces.std.Handshaked - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.amba.datapump.intf.AxiWDatapumpIntfAgent(sim: HdlSimulator, intf)[source]¶

Bases: AgentBase

Composite agent with agent for every AxiRDatapumpIntf channel enable is shared

__init__(sim: HdlSimulator, intf)[source]¶

property enable¶

getDrivers()[source]¶: Called before simulation to collect all drivers of interfaces from this agent

getMonitors()[source]¶: Called before simulation to collect all monitors of interfaces from this agent

hwtLib.amba.datapump.r module¶

class hwtLib.amba.datapump.r.Axi_rDatapump(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶

Bases: AxiDatapumpBase

Forward request to axi address read channel and collect data to data channel form axi read data channel

Blocks data channel when there is no request pending.
If req len is wider transaction is internally split to multiple axi transactions, but returned read data is a single packet as originally requested.
errorRead stays high when there was error on axi read channel it will not affect unit functionality
id of driver is a different id than is used on AXI this is because the id on driver side is used to distinguish between transactions and on AXI side it has to be same to assert that the transactions will be finished in-order.

HDL params

MAX_TRANS_OVERLAP - default value 16 of type int
ALIGNAS - default value 8 of type int
CHUNK_WIDTH - default value 64 of type int
MAX_CHUNKS - default value 64 of type int
ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
USER_WIDTH - default value 0 of type int
ADDR_USER_VAL - default value None of type None
DATA_WIDTH - default value 64 of type int
ID_VAL - default value 0 of type int
CACHE_VAL - default value 3 of type int
PROT_VAL - default value 0 of type int
QOS_VAL - default value 0 of type int
USE_STRB - default value True of type bool
AXI_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
axi - of type hwtLib.amba.axi4.Axi4 - MASTER
errorRead - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
driver - of type hwtLib.amba.datapump.intf.AxiRDatapumpIntf - SLAVE

HDL components

sizeRmFifo - of type hwtLib.handshaked.fifo.HandshakedFifo
aligner - of type hwtLib.amba.axis_comp.frame_join._join.AxiS_FrameJoin

schematic

dataHandler(rErrFlag: RtlSignal, rmSizeOut: TransEndInfo)[source]¶

remSizeToStrb(remSize: RtlSignal, strb: RtlSignal, isFirstWord, isLastWord)[source]¶

storeTransInfo(transInfo: TransEndInfo, isLast: bool)[source]¶

class hwtLib.amba.datapump.r.TransEndInfo(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: HandshakeSync

HDL params

ID_WIDTH - default value 0 of type int
DATA_WIDTH - default value 64 of type int
HAS_PROPAGATE_LAST - default value True of type bool
SHIFT_OPTIONS - default value (0,) of type tuple

HDL IO

rem - of type hwt.interfaces.std.Signal with dtype=<Bits, 3bits> - MASTER
propagateLast - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

hwtLib.amba.datapump.sim_ram module¶

class hwtLib.amba.datapump.sim_ram.AxiDpSimRam(cellWidth, clk, rDatapumpIntf=None, wDatapumpIntf=None, parent=None)[source]¶

Bases: SimRam

Dense RAM for simulation purposes with axi datapump interfaces

Variables: ~.data – memory dict

__init__(cellWidth, clk, rDatapumpIntf=None, wDatapumpIntf=None, parent=None)[source]¶

Parameters

cellWidth – width of items in memmory
clk – clk signal for synchronization
parent – parent instance of SimRam (memory will be shared with this instance)

_registerOnClock()[source]¶

checkRequests()[source]¶: Check if any request has appeared on interfaces

doRead()[source]¶

doWrite()[source]¶

doWriteAck(_id)[source]¶

onReadReq()[source]¶

onWriteReq()[source]¶

parseReq(req)[source]¶

hwtLib.amba.datapump.utils module¶

hwtLib.amba.datapump.utils.connectDp(parent, controller, datapump, axi, exclude=None)[source]¶

Connect datapump with it’s controller(s) and axi

Parameters

controller – (controller compatible with Axi_wDatapump or Axi_rDatapump) or list/tuple/generator of them
datapump – Axi_wDatapump or Axi_rDatapump
axi – axi(3/4) interface which datapump should use

hwtLib.amba.datapump.w module¶

class hwtLib.amba.datapump.w.Axi_wDatapump(axiCls=<class 'hwtLib.amba.axi4.Axi4'>)[source]¶

Bases: AxiDatapumpBase

Axi3/Axi3Lte/Axi4/Axi4Lite to axi write datapump,

HDL params

MAX_TRANS_OVERLAP - default value 16 of type int
ALIGNAS - default value 8 of type int
CHUNK_WIDTH - default value 64 of type int
MAX_CHUNKS - default value 64 of type int
ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
USER_WIDTH - default value 0 of type int
ADDR_USER_VAL - default value None of type None
DATA_WIDTH - default value 64 of type int
ID_VAL - default value 0 of type int
CACHE_VAL - default value 3 of type int
PROT_VAL - default value 0 of type int
QOS_VAL - default value 0 of type int
USE_STRB - default value True of type bool
AXI_CLS - default value <class ‘hwtLib.amba.axi4.Axi4’> of type type

HDL IO

clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
axi - of type hwtLib.amba.axi4.Axi4 - MASTER
errorWrite - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
driver - of type hwtLib.amba.datapump.intf.AxiWDatapumpIntf - SLAVE

HDL components

writeInfoFifo - of type hwtLib.handshaked.fifo.HandshakedFifo
bInfoFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

axiBHandler()[source]¶

axiWHandler(wErrFlag: RtlSignal)[source]¶

storeTransInfo(transInfo: WFifoIntf, isLast: bool)[source]¶

class hwtLib.amba.datapump.w.BFifoIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

HDL IO

isLast - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶

class hwtLib.amba.datapump.w.WFifoIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]¶

Bases: Handshaked

HDL params

SHIFT_OPTIONS - default value (0,) of type tuple

HDL IO

vld - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER
rd - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE (Master=IN)

_initSimAgent(sim: HdlSimulator)[source]¶