hwtLib.amba.axi_comp.oooOp package

This package is dedicated to components and other utilities for out-of-order processing.


hwtLib.amba.axi_comp.oooOp.outOfOrderCummulativeOp module

class hwtLib.amba.axi_comp.oooOp.outOfOrderCummulativeOp.OutOfOrderCummulativeOp(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Out of order container of read-modify-write cummulative operation.

This is a component template for cumulative Out of Order operations with hihgh latency AXI. Suitable for counter arrays, hash tables and other data structures which are acessing data randomly and potential collision due read-modify-write operations may occure.

This component stores info about currently executed memory transactions which may be finished out of order. Potential memory access colisions are solved by write forwarding in main pipeline. In order to compensate for memory write latency the write history is utilised. The write history is a set of registers on the end of the pipeline.

Note that the write history is not meant as a main mechanism for write latency compensation. It is meant to be used for 3-4 items to componsate for latency of the cache/LSU.

If the main operation requires multiple clock cycles the operation is performed speculatively.

The most up-to-date version of the data is always selected on the input of WRITE_BACK stage.

  • MAIN_STATE_T – a type of the state in main memory which is being updated by this component

  • TRANSACTION_STATE_T – a type of the transaction state, used to store additional data for transaction and can be used to modify the behavior of the pipeline


If MAIN_STATE_T.bit_length() is smaller than DATA_WIDTH each item is allocated in a signle bus word separately in order to avoid alignment logic

_axi_addr_defaults(a: hwtLib.amba.axi4.Axi4_addr)[source]

Set default values for AXI address channel signals

apply_data_write_forwarding(st: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage, st_load_en: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, data_modifier=<function OutOfOrderCummulativeOp.<lambda>>)[source]

st_collision_detect – in format stages X pipeline[WRITE_BACK-1:], if bit = 1 it means that the stage data should be updated from stage on that index


Send read request on AXI and store transaction in to state array and ooo_fifo for later wake up

collision_detector(pipeline: List[hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage]) List[List[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal]][source]

Search for address access collisions in pipeline and store the result of colision check to registers for data write forwarding in next clock tick

data_load(r: hwtLib.amba.axi4.Axi4_r, st0: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage)[source]
data_store(st_data: Union[hwt.interfaces.structIntf.StructIntf, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], w: hwtLib.amba.axi4.Axi4_w, ack: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)[source]

ack – signal which is 1 if the data word is transfered on this write channel

instruction_supports_forwarding(st: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage)[source]
main_op(main_state: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal) hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]
propagate_trans_st(stage_from: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage, stage_to: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage)[source]
write_cancel(st: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage)[source]

A signal/value which if it is 1 it means that the write back of this state should not be performed.

hwtLib.amba.axi_comp.oooOp.utils module

class hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage(index, name: str, parent: OutOfOrderCummulativeOp)[source]

Bases: object

  • index – index of the register in pipeline

  • id – an id of an axi transaction (and index of item in state_array)

  • addr – an address which is beeing processed in this stage

  • state – state loaded from the state_array (current meta state)

  • data – currently loaded data from the bus

  • valid – validity flag for whole stage

  • ready – if 1 the stage can recieve data on next clock edge, otherwise the stage stalls

  • collision_detect – the list of flags (sotored in register) if flag is 1 it means that the value should be updated from stage on that index

  • load_en – if 1 the stage will load the data from previous stage in this clock cycle

__init__(index, name: str, parent: OutOfOrderCummulativeOp)[source]

Return repr(self).

class hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.Handshaked

HDL params
  • TRANSACTION_STATE_T - default value <Bits, 8bits, unsigned> of type hwt.hdl.types.bits.Bits

  • MAIN_STATE_T - default value <Bits, 8bits, unsigned> of type hwt.hdl.types.bits.Bits

  • MAIN_STATE_INDEX_WIDTH - default value 8 of type int

_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpIntfAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf: hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpIntf, allowNoReset=False)[source]

Bases: hwt.interfaces.agents.handshaked.HandshakedAgent


if TRANSACTION_STATE_T is None the data should be only int for address else data should be tuple of int for address and a value of the state state value depends on state type, for simple bit vector it is just int, for struct it is tuple, …

__init__(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf: hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpIntf, allowNoReset=False)[source]

rst – tuple (rst signal, rst_negated flag)


Called before simulation to collect all drivers of interfaces from this agent


Called before simulation to collect all monitors of interfaces from this agent


extract data from interface


write data to interface

class hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpPipelineConfig(READ_DATA_RECEIVE, STATE_LOAD, WRITE_BACK, WAIT_FOR_WRITE_ACK, WRITE_HISTORY_SIZE)[source]

Bases: tuple


Alias for field number 0


Alias for field number 1


Alias for field number 3


Alias for field number 2


Alias for field number 4

__annotations__ = {'READ_DATA_RECEIVE': <class 'int'>, 'STATE_LOAD': <class 'int'>, 'WAIT_FOR_WRITE_ACK': <class 'int'>, 'WRITE_BACK': <class 'int'>, 'WRITE_HISTORY_SIZE': <class 'int'>}

Return self as a plain tuple. Used by copy and pickle.

static __new__(_cls, READ_DATA_RECEIVE: int, STATE_LOAD: int, WRITE_BACK: int, WAIT_FOR_WRITE_ACK: int, WRITE_HISTORY_SIZE: int)



Return a nicely formatted representation string

__slots__ = ()

Return a new dict which maps field names to their values.

_field_defaults = {}
_field_types = {'READ_DATA_RECEIVE': <class 'int'>, 'STATE_LOAD': <class 'int'>, 'WAIT_FOR_WRITE_ACK': <class 'int'>, 'WRITE_BACK': <class 'int'>, 'WRITE_HISTORY_SIZE': <class 'int'>}
_fields_defaults = {}
classmethod _make(iterable)

Make a new OutOfOrderCummulativeOpPipelineConfig object from a sequence or iterable


Return a new OutOfOrderCummulativeOpPipelineConfig object replacing specified fields with new values

classmethod new_config(WRITE_TO_WRITE_ACK_LATENCY: int, WRITE_ACK_TO_READ_DATA_LATENCY: int)[source]
hwtLib.amba.axi_comp.oooOp.utils.does_collinde(st0: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage, st1: hwtLib.amba.axi_comp.oooOp.utils.OOOOpPipelineStage)[source]