hwtLib.amba.datapump.interconnect package¶
Submodules¶
hwtLib.amba.datapump.interconnect.rStricOrder module¶
- class hwtLib.amba.datapump.interconnect.rStricOrder.RStrictOrderInterconnect(hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiInterconnectBase
Strict order interconnect for AxiRDatapumpIntf (N-to-1) ensures that response on request is delivered to driver which asked for it while transactions can overlap
- HDL params
DRIVER_CNT - default value 2 of type int
MAX_TRANS_OVERLAP - default value 16 of type int
ID_WIDTH - default value 0 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_BYTES - default value 4096 of type int
USE_STRB - default value True of type bool
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
drivers_0 - of type hwtLib.amba.datapump.intf.AxiRDatapumpIntf - SLAVE
drivers_1 - of type hwtLib.amba.datapump.intf.AxiRDatapumpIntf - SLAVE
rDatapump - of type hwtLib.amba.datapump.intf.AxiRDatapumpIntf - MASTER
- HDL components
orderInfoFifo - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinFair.HsJoinFairShare
hwtLib.amba.datapump.interconnect.wStrictOrder module¶
- class hwtLib.amba.datapump.interconnect.wStrictOrder.WStrictOrderInterconnect(hdl_name_override: Optional[str] = None)[source]¶
Bases:
AxiInterconnectBase
Strict order interconnect for AxiWDatapumpIntf (N-to-1) ensures that response on request is delivered to driver which asked for it while transactions can overlap
- HDL params
DRIVER_CNT - default value 2 of type int
MAX_TRANS_OVERLAP - default value 16 of type int
ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_LEN - default value 511 of type int
USE_STRB - default value True of type bool
- HDL IO
clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE
rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE
drivers_0 - of type hwtLib.amba.datapump.intf.AxiWDatapumpIntf - SLAVE
drivers_1 - of type hwtLib.amba.datapump.intf.AxiWDatapumpIntf - SLAVE
wDatapump - of type hwtLib.amba.datapump.intf.AxiWDatapumpIntf - MASTER
- HDL components
orderInfoFifoW - of type hwtLib.handshaked.fifo.HandshakedFifo
orderInfoFifoAck - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinFair.HsJoinFairShare