hwtLib.amba.datapump.interconnect package

Submodules

hwtLib.amba.datapump.interconnect.rStricOrder module

class hwtLib.amba.datapump.interconnect.rStricOrder.RStrictOrderInterconnect(hdlName: str | None = None)

Bases: AxiInterconnectBase

Strict order interconnect for HwIOAxiRDatapump (N-to-1) ensures that response on request is delivered to driver which asked for it while transactions can overlap

HDL params:

• DRIVER_CNT - default value 2 of type int

• MAX_TRANS_OVERLAP - default value 16 of type int

• ID_WIDTH - default value 0 of type int

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

• MAX_BYTES - default value 4096 of type int

• USE_STRB - default value True of type bool

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• drivers - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

• rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER

HDL components:

• orderInfoFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

• gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinFair.HsJoinFairShare

schematic

__annotations__ = {}

getDpHwIO(unit)

hwtLib.amba.datapump.interconnect.wStrictOrder module

class hwtLib.amba.datapump.interconnect.wStrictOrder.WStrictOrderInterconnect(hdlName: str | None = None)

Bases: AxiInterconnectBase

Strict order interconnect for HwIOAxiWDatapump (N-to-1) ensures that response on request is delivered to driver which asked for it while transactions can overlap

HDL params:

• DRIVER_CNT - default value 2 of type int

• MAX_TRANS_OVERLAP - default value 16 of type int

• ID_WIDTH - default value 4 of type int

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

• MAX_LEN - default value 511 of type int

• USE_STRB - default value True of type bool

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• drivers - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE

• wDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiWDatapump - MASTER

HDL components:

• orderInfoFifoW - of type hwtLib.handshaked.fifo.HandshakedFifo

• orderInfoFifoAck - of type hwtLib.handshaked.fifo.HandshakedFifo

• gen_join_gen_join_join_0 - of type hwtLib.handshaked.joinFair.HsJoinFairShare

schematic

__annotations__ = {}

ackHandler()

getDpHwIO(unit)

wHandler()