hwtLib.logic package¶

Submodules¶

hwtLib.logic.bcdToBin module¶

class hwtLib.logic.bcdToBin.BcdToBin(hdlName: str | None = None)[source]¶

Bases: HwModule

Convert a BCD number to binary encoding This uses the double-dabble algorithm in reverse. The conversion of a BCD number to an n-bit binary number will take n+3 cycles to complete.

based on: https://github.com/kevinpt/vhdl-extras/blob/master/rtl/extras/bcd_conversion.vhdl

HDL params:

BCD_DIGITS - default value 3 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
din - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
dout - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}¶

hwtLib.logic.binToBcd module¶

class hwtLib.logic.binToBcd.BinToBcd(hdlName: str | None = None)[source]¶

Bases: HwModule

Convert binary to BCD (Binary coded decimal) format (BCD is a format where each 4 bites represents a single decimal digit 0-9)

based on https://github.com/kb000/bin2bcd/blob/master/rtl/bin2bcd32.v

HDL params:

INPUT_WIDTH - default value 64 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
din - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
dout - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

schematic

__annotations__ = {}¶

static decadic_deciamls_for_bin(bin_width: int)[source]¶

hwtLib.logic.binToOneHot module¶

class hwtLib.logic.binToOneHot.BinToOneHot(hdlName: str | None = None)[source]¶

Bases: HwModule

Little endian encoded number to number in one-hot encoding

HDL params:

DATA_WIDTH - default value 8 of type int

HDL IO:

din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 3bits> - SLAVE
en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE
dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.binToOneHot.BinToOneHotTC(methodName='runTest')[source]¶

Bases: SimTestCase

__annotations__ = {}¶

_classSetupFailed = False¶

_class_cleanups = []¶

classmethod setUpClass()[source]¶: Hook method for setting up class fixture before running tests in the class.

test_basic()[source]¶

hwtLib.logic.binToOneHot.binToOneHot(sig, en=1)[source]¶

hwtLib.logic.bitonicSorter module¶

class hwtLib.logic.bitonicSorter.BitonicSorter(cmpFn=<function BitonicSorter.<lambda>>)[source]¶

Bases: HwModule

Bitonic sorter of arbitrary data

HDL params:

ITEMS - default value 2 of type int
DATA_WIDTH - default value 64 of type int
SIGNED - default value False of type bool

HDL IO:

inputs - of type hwt.hwIOs.hwIOArray.HwIOArray - SLAVE
outputs - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

schematic

__annotations__ = {}¶

__init__(cmpFn=<function BitonicSorter.<lambda>>)[source]¶

Parameters:: cmpFn – function (item0, item1) if returns true, items are not swaped

bitonic_compare(cmpFn, x, layer, offset)[source]¶

bitonic_merge(cmpFn, x, layer, offset)[source]¶

bitonic_sort(cmpFn, x, layer=0, offset=0)[source]¶

class hwtLib.logic.bitonicSorter.BitonicSorterTC(methodName='runTest')[source]¶

Bases: SimTestCase

SIM_TIME = 40000¶

__annotations__ = {}¶

_classSetupFailed = False¶

_class_cleanups = []¶

getOutputs()[source]¶

setInputs(values)[source]¶

classmethod setUpClass()[source]¶: Hook method for setting up class fixture before running tests in the class.

test_reversed()[source]¶

test_sorted()[source]¶

hwtLib.logic.cntrGray module¶

class hwtLib.logic.cntrGray.GrayCntr(hdlName: str | None = None)[source]¶

Bases: HwModule

Counter for gray code

HDL params:

DATA_WIDTH - default value 4 of type int
INIT_VAL - default value 0 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE
dataOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.cntrGray.GrayCntrTC(methodName='runTest')[source]¶

Bases: SimTestCase

__annotations__ = {}¶

_classSetupFailed = False¶

_class_cleanups = []¶

classmethod setUpClass() → HwModule[source]¶: Hook method for setting up class fixture before running tests in the class.

test_count()[source]¶

hwtLib.logic.cntrGray.binToGray(sigOrConst) → RtlSignalBase[source]¶: Convert value or signal from binary encoding to gray encoding

hwtLib.logic.countLeading module¶

class hwtLib.logic.countLeading.CountLeadingOnes(hdlName: str | None = None)[source]¶

Bases: _CountLeading

Count leading zeros in bit vector (leading means from MSB side)

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

data_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE
data_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.countLeading.CountLeadingZeros(hdlName: str | None = None)[source]¶

Bases: _CountLeading

Count leading zeros in bit vector (leading means from MSB side)

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

data_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE
data_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.countLeading.CountTrailingOnes(hdlName: str | None = None)[source]¶

Bases: _CountLeading

Count trailing zeros in bit vector (trailing means from LSB side)

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

data_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE
data_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.countLeading.CountTrailingZeros(hdlName: str | None = None)[source]¶

Bases: _CountLeading

Count trailing zeros in bit vector (trailing means from LSB side)

HDL params:

DATA_WIDTH - default value 2 of type int

HDL IO:

data_in - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE
data_out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - MASTER

schematic

__annotations__ = {}¶

class hwtLib.logic.countLeading._CountLeading(hdlName: str | None = None)[source]¶

Bases: HwModule

Count leading zeros/ones in bit vector

__annotations__ = {}¶

hwtLib.logic.countLeading._countLeadingRecurse(dataIn: RtlSignalBase[HBits], bitValToCount: int) → HBitsRtlSignal | HBitsConst[source]¶

Construct a balanced tree for counter of leading 0/1

Attention:: result is not final result, it is only for 0 to width-1 values

hwtLib.logic.countLeading._countTrailingRecurse(dataIn: RtlSignalBase[HBits], bitValToCount: int) → HBitsRtlSignal | HBitsConst[source]¶: Version of _countLeadingRecurse() which counts from the back of the vector (upper bits first)

hwtLib.logic.countLeading.countBits(dataIn: RtlSignalBase[HBits], bitValToCount: int, leading: bool) → HBitsRtlSignal | HBitsConst[source]¶

Parameters:

bitValToCount – parameter to switch between count of zeros and ones
leading – flag which switches between leading (from MSB side) and trailing (from LSB side) count

Returns:

number of bits set to bitValToCount value

hwtLib.logic.crc module¶

class hwtLib.logic.crc.Crc(hdlName: str | None = None)[source]¶

Bases: HwModule

Crc generator for any crc, polynome can be string in usual format or integer (“x^3+x+1” or 0b1011)

HDL params:

DATA_WIDTH - default value 24 of type intnumber of bits of data in
IN_IS_BIGENDIAN - default value False of type bool
POLY_TY - default value <class ‘hwtLib.logic.crcPoly.CRC_32’> of type type
LATENCY - default value 1 of type intnumber of cycles from data in to data out
MASK_GRANULARITY - default value 8 of type intif None, there is no mask for data in, else it must be an int which represents number of bits per 1 bit of mask signal, this allows this component to compute crc for smaller bitwidth than data_in width
CONTAINS_STATE_REG - default value True of type boolif True the state register is present in this component otherwise the stateIn io is used as a value of current sate

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
dataIn - of type hwtLib.commonHwIO.data_mask_last_hs.HwIODataMaskLastRdVld - SLAVE
dataOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

schematic

__annotations__ = {}¶

_aply_REFOUT_and_XOROUT(state: RtlSignal, POLY_WIDTH: int, REFOUT: bool, XOROUT: int)[source]¶

build_crc_xor_matrix(state_in_bits: List[RtlSignal], poly_bits: List[int], data_in_bits: List[RtlSignal]) → List[RtlSignal][source]¶: build xor tree for CRC computation

setConfig(crcConfigCls)[source]¶: Apply configuration from CRC configuration class

hwtLib.logic.crc._example_Crc()[source]¶

hwtLib.logic.crcComb module¶

class hwtLib.logic.crcComb.CrcComb(hdlName: str | None = None)[source]¶

Bases: HwModule

CRC generator, polynomial can be string in usual format or integer (“x^3+x+1” or 0b1011)

Variables:

~.DATA_WIDTH – width of data in signal
~.POLY – specified CRC polynome, str, int or HBits value
~.POLY_WIDTH – width of POLY
~.REFIN – This is a boolean parameter. If it is FALSE, input bytes are processed with bit 7 being treated as the most significant bit (MSB) and bit 0 being treated as the least significant bit. If this parameter is FALSE, each byte is reflected before being processed.
~.REFOUT – Same as REFIN except for output
~.XOROUT – value to xor result with

HDL params:

DATA_WIDTH - default value 11 of type int
IN_IS_BIGENDIAN - default value False of type bool
POLY_TY - default value <class ‘hwtLib.logic.crcPoly.CRC_5_USB’> of type type

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
dataIn - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 11bits> - SLAVE
dataOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 5bits> - MASTER

schematic

__annotations__ = {}¶

classmethod applyCrcXorMatrix(crcMatrix: List[List[List[int]]], inBits: List[RtlSignal], stateBits: List[RtlSignal | HBitsConst], refin: bool) → List[source]¶

static buildCrcXorMatrix(data_width: int, polyBits: List[bool]) → List[Tuple[List[bool], List[bool]]][source]¶

Parameters:

data_width – number of bits in input (excluding bits of signal wit current crc state)
polyBits – list of bits in specified polynome

Note:

all bits are in format LSB downto MSB

Returns:

crc_mask contains rows where each row describes which bits should be XORed to get bit of result row is [mask_for_state_reg, mask_for_data]

static parsePoly(POLY: int, POLY_WIDTH: int) → List[int][source]¶

Returns:: list of bits from polynome, extra MSB 1 is added len of this list is POLY_WIDTH + 1

setConfig(crcConfigCls: Tuple[CRC_POLY])[source]¶: Apply configuration from CRC configuration class

hwtLib.logic.crcPoly module¶

Library of common CRC configurations

note:: POLY is the polynome of CRC and specifies which bits should be xored together.
note:: WIDTH - specifies the width of CRC state/value
note:: REFIN - If it is True the bits in each byte are reversed before processing.
note:: REFOUT If it is set to FALSE, the final value in the register is fed into the XOROUT stage directly, otherwise, if this parameter is TRUE, the final register value is reflected first.
note:: XOROUT This is an WIDTH-bit value. It is XORed to the final register value (after the REFOUT) stage before the value is returned as the official checksum.
note:: http://reveng.sourceforge.net/crc-catalogue/all.htm
note:: https://github.com/nanpuyue/crc/blob/master/CRC.txt

class hwtLib.logic.crcPoly.CRC3_ROHC[source]¶

hwtLib.logic package¶

Submodules¶

hwtLib.logic.bcdToBin module¶

hwtLib.logic.binToBcd module¶

hwtLib.logic.binToOneHot module¶

hwtLib.logic.bitonicSorter module¶

hwtLib.logic.cntrGray module¶

hwtLib.logic.countLeading module¶

hwtLib.logic.crc module¶

hwtLib.logic.crcComb module¶

hwtLib.logic.crcPoly module¶

hwtLib.logic.crcUtils module¶

hwtLib.logic.crc_test_utils module¶

hwtLib.logic.lfsr module¶

hwtLib.logic.oneHotToBin module¶

hwtLib.logic.pid module¶

hwtLib.logic.rtlSignalBuilder module¶