hwtLib.structManipulators package¶

Submodules¶

hwtLib.structManipulators.arrayBuff_writer module¶

class hwtLib.structManipulators.arrayBuff_writer.ArrayBuff_writer(hdlName: str | None = None)[source]¶

Bases: HwModule

Write data in to a circula buffer allocated as an array. Collect items and send them over wDatapump when buffer is full or on timeout Maximum overlap of transactions is 1

items -> buff -> internal logic -> axi datapump

HDL params:

ID_WIDTH - default value 4 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_LEN - default value 15 of type int
USE_STRB - default value True of type bool
ID - default value 3 of type int
ITEM_WIDTH - default value 16 of type int
BUFF_DEPTH - default value 16 of type int
TIMEOUT - default value 1024 of type int
ITEMS - default value 512 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
items - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
wDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiWDatapump - MASTER
uploaded - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - MASTER
baseAddr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE
buff_remain - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - MASTER

HDL components:

buff - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

uploadedCntrHandler(st, reqAckHasCome, sizeOfitems)[source]¶

hwtLib.structManipulators.arrayItemGetter module¶

class hwtLib.structManipulators.arrayItemGetter.ArrayItemGetter(hdlName: str | None = None)[source]¶

Bases: HwModule

Get specific item from array by index

HDL params:

ITEMS - default value 32 of type int
ITEM_WIDTH - default value 32 of type int
ID - default value 0 of type int
ID_WIDTH - default value 4 of type int
DATA_WIDTH - default value 64 of type int
ADDR_WIDTH - default value 32 of type int
MAX_TRANS_OVERLAP - default value 16 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
base - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - SLAVE
index - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
item - of type hwt.hwIOs.std.HwIODataRdVld - MASTER
rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER

HDL components:

itemSubIndexFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

hwtLib.structManipulators.cLinkedListReader module¶

class hwtLib.structManipulators.cLinkedListReader.CLinkedListReader(hdlName: str | None = None)[source]¶

Bases: HwModule

This unit reads items from (circular) linked list like structure

struct node {
    item_t items[ITEMS_IN_BLOCK],
    struct node * next;
};

synchronization is obtained by rdPtr/wrPtr (tail/head) pointer baseAddr is address of actual node

HDL params:

ID_WIDTH - default value 4 of type int
ID - default value 3 of type int
ID_LAST - default value 4 of type int
BUFFER_CAPACITY - default value 32 of type int
ITEMS_IN_BLOCK - default value 511 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
PTR_WIDTH - default value 16 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER
dataOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER
inBlockRemain - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 9bits> - MASTER
baseAddr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE
rdPtr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE
wrPtr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE

HDL components:

dataFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

addrAlignBits()[source]¶

hwtLib.structManipulators.cLinkedListWriter module¶

class hwtLib.structManipulators.cLinkedListWriter.CLinkedListWriter(hdlName: str | None = None)[source]¶

Bases: HwModule

This unit writes items to (circular) linked list like structure (List does not necessary need to be circular but space is specified by two pointers like in circular queue)

struct node {
    item_t items[ITEMS_IN_BLOCK],
    struct node * next;
};

synchronization is obtained by rdPtr/wrPtr (tail/head) pointer baseAddr is address of actual node

HDL params:

ID_WIDTH - default value 4 of type int
ID - default value 3 of type int
BUFFER_CAPACITY - default value 32 of type int
ITEMS_IN_BLOCK - default value 511 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
PTR_WIDTH - default value 16 of type int
TIMEOUT - default value 4096 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER
wDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiWDatapump - MASTER
dataIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
baseAddr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE
rdPtr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE
wrPtr - of type hwt.hwIOs.std.HwIORegCntrl - SLAVE

HDL components:

dataFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

addrToIndex(addr)[source]¶

baseAddrLogic(nextBlockTransition_in)[source]¶

Logic for downloading address of next block

Parameters:: nextBlockTransition_in – signal which means that baseIndex should be changed to nextBaseIndex if nextBaseAddrReady is not high this signal has no effect (= regular handshake)
Returns:: (baseIndex, nextBaseIndex, nextBaseReady is ready and nextBlockTransition_in can be used)

indexToAddr(indx)[source]¶

itemUploadLogic(baseIndex, nextBaseIndex, nextBaseReady, nextBlockTransition_out)[source]¶

mvDataToW(prepareEn, dataMoveEn, reqLen, inBlockRemain, nextBlockTransition_out, dataCntr_out)[source]¶

queuePtrLogic(wrPtrIncrVal, wrPtrIncrEn)[source]¶

rReqHandler(baseIndex, doReq)[source]¶

timeoutHandler(rst, incr)[source]¶

wReqDriver(en, baseIndex, lenByPtrs, inBlockRemain)[source]¶

hwtLib.structManipulators.mmu_2pageLvl module¶

class hwtLib.structManipulators.mmu_2pageLvl.MMU_2pageLvl(hdlName: str | None = None)[source]¶

Bases: HwModule

MMU where parent page table is stored in ram this unit and only items from leaf page tables are download on each request over rDatapump interface

HDL params:

ID_WIDTH - default value 1 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
VIRT_ADDR_WIDTH - default value 32 of type int
LVL1_PAGE_TABLE_ITEMS - default value 512 of type int
PAGE_SIZE - default value 4096 of type int
MAX_OVERLAP - default value 16 of type int

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER
virtIn - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
physOut - of type hwt.hwIOs.std.HwIODataRdVld - MASTER
segfault - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER
lvl1Table - of type hwt.hwIOs.std.HwIOBramPort_noClk - SLAVE

HDL components:

lvl1Storage - of type hwtLib.mem.ram.RamSingleClock
lvl1Converter - of type hwtLib.handshaked.ramAsAddrDataRdVld.RamAsAddrDataRdVld
lvl2get - of type hwtLib.structManipulators.arrayItemGetter.ArrayItemGetter
lvl2indxFifo - of type hwtLib.handshaked.fifo.HandshakedFifo
pageOffsetFifo - of type hwtLib.handshaked.fifo.HandshakedFifo

schematic

__annotations__ = {}¶

connectL1Load(lvl1readAddr)[source]¶

connectL2Load(lvl2base, segfaultFlag)[source]¶

connectLvl1PageTable()[source]¶

connectPhyout(segfaultFlag)[source]¶

segfaultChecker()[source]¶

hwtLib.structManipulators.structReader module¶

class hwtLib.structManipulators.structReader.StructReader(structT, tmpl=None, frames=None)[source]¶

Bases: Axi4S_frameParser

This unit downloads required structure fields over rDatapump interface from address specified by get interface

Variables:

~.ID – HwParam, id for transactions on bus
~.READ_ACK – HwParam, if true ready on “get” will be set only when component is in idle (if false “get” is regular handshaked interface)
~.SHARED_READY – HwParam, if this is true field interfaces will be of type VldSynced and single ready signal will be used for all else every interface will be instance of HwIODataRdVld and it will have it’s own ready(rd) signal

HDL params:

ID - default value 0 of type int
ID_WIDTH - default value 0 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_BYTES - default value 4096 of type int
USE_STRB - default value False of type bool
READ_ACK - default value False of type bool
SHARED_READY - default value False of type bool

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
dataOut - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 64bits, unsigned> item0 //<HBits, 64bits, unsigned> empty space <HBits, 64bits, unsigned> item1 //<HBits, 64bits, unsigned> empty space <HBits, 16bits, unsigned> item2 <HBits, 16bits, unsigned> item3 <HBits, 32bits, unsigned> item4 //<HBits, 32bits, unsigned> empty space <HBits, 64bits, unsigned> item5 //<HBits, 32bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space <HBits, 64bits, unsigned> item6 <HBits, 64bits, unsigned> item7 } - MASTER
get - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
rDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiRDatapump - MASTER

HDL components:

parser - of type hwtLib.amba.axis_comp.frame_parser._parser.Axi4S_frameParser
gen_get_reg_0 - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__annotations__ = {}¶

__init__(structT, tmpl=None, frames=None)[source]¶

Parameters:

structT – instance of HStruct which specifies data format to download
tmpl – instance of TransTmpl for this structT
frames – list of FrameTmpl instances for this tmpl

Note:

if tmpl and frames are None they are resolved from structT parseTemplate

Note:

this unit can parse sequence of frames, if they are specified by “frames”

Attention:

interfaces for each field in struct will be dynamically created

Attention:

structT can not contain fields with variable size like HStream

driveReqRem(req: AddrSizeHs, MAX_BITS: int)[source]¶

maxBytesInTransaction()[source]¶

maxWordIndex()[source]¶

parseTemplate()[source]¶: Load the configuration from the parameters

hwtLib.structManipulators.structReader._example_StructReader()[source]¶

hwtLib.structManipulators.structWriter module¶

class hwtLib.structManipulators.structWriter.StructWriter(structT, tmpl=None, frames=None)[source]¶

Bases: StructReader

Write struct specified in constructor over wDatapump interface on address specified over set interface

Variables:

~.MAX_OVERLAP – parameter which specifies the maximum number of concurrent transaction
~.WRITE_ACK – HwParam, if true ready on “set” will be set only when component is in idle (if false “set” is regular handshaked interface)

HDL params:

ID - default value 0 of type int
ID_WIDTH - default value 0 of type int
ADDR_WIDTH - default value 32 of type int
DATA_WIDTH - default value 64 of type int
MAX_BYTES - default value 4096 of type int
USE_STRB - default value False of type bool
READ_ACK - default value False of type bool
SHARED_READY - default value False of type bool
MAX_OVERLAP - default value 2 of type int
WRITE_ACK - default value False of type bool

HDL IO:

clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE
rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE
dataIn - of type hwt.hwIOs.hwIOStruct.HwIOStruct with dtype=struct { <HBits, 64bits, unsigned> item0 //<HBits, 64bits, unsigned> empty space <HBits, 64bits, unsigned> item1 //<HBits, 64bits, unsigned> empty space <HBits, 16bits, unsigned> item2 <HBits, 16bits, unsigned> item3 <HBits, 32bits, unsigned> item4 //<HBits, 32bits, unsigned> empty space <HBits, 64bits, unsigned> item5 //<HBits, 32bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space //<HBits, 64bits, unsigned> empty space <HBits, 64bits, unsigned> item6 <HBits, 64bits, unsigned> item7 } - SLAVE
set - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE
writeAck - of type hwt.hwIOs.std.HwIORdVldSync - MASTER
wDatapump - of type hwtLib.amba.datapump.intf.HwIOAxiWDatapump - MASTER

HDL components:

frameAssember - of type hwtLib.amba.axis_comp.frame_deparser._deparser.Axi4S_frameDeparser
ackPropageteInfo - of type hwtLib.handshaked.fifo.HandshakedFifo
gen_set_reg_0 - of type hwtLib.handshaked.reg.HandshakedReg

schematic

__annotations__ = {}¶

_createInterfaceForField(parent, structField)[source]¶

hwtLib.structManipulators.structWriter._example_StructWriter()[source]¶