hwtLib.examples package

This module is a collection of examples. Examples usually do have 2 purposes. First is to demostrate the functionality. Second is to test it.

Subpackages

Submodules

hwtLib.examples.base_serialization_TC module

class hwtLib.examples.base_serialization_TC.BaseSerializationTC(methodName='runTest')[source]

Bases: SimTestCase

SERIALIZER_BY_EXT = {'cpp': <class 'hwt.serializer.systemC.SystemCSerializer'>, 'py': <class 'hwt.serializer.hwt.HwtSerializer'>, 'v': <class 'hwt.serializer.verilog.VerilogSerializer'>, 'vhd': <class 'hwt.serializer.vhdl.Vhdl2008Serializer'>}
__FILE__ = None
assert_same_as_file(s, file_name: str)[source]
assert_serializes_as_file(u: Unit, file_name: str)[source]
strStructureCmp(cont, tmpl)[source]
tearDown()[source]

Hook method for deconstructing the test fixture after testing it.

hwtLib.examples.emptyUnitWithSpi module

class hwtLib.examples.emptyUnitWithSpi.EmptyUnitWithSpi(hdl_name_override: Optional[str] = None)[source]

Bases: EmptyUnit

class hwtLib.examples.emptyUnitWithSpi.EmptyUnitWithSpiTC(methodName='runTest')[source]

Bases: BaseSerializationTC

__FILE__ = '/home/docs/checkouts/readthedocs.org/user_builds/hwtlib/checkouts/latest/hwtLib/examples/emptyUnitWithSpi.py'
test_vhdl()[source]

hwtLib.examples.hdlComments module

class hwtLib.examples.hdlComments.SimpleComentedUnit(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment. Do not forget that class inheritance does apply for docstring as well.

class hwtLib.examples.hdlComments.SimpleComentedUnit2(hdl_name_override: Optional[str] = None)[source]

Bases: SimpleComentedUnit

single line

class hwtLib.examples.hdlComments.SimpleComentedUnit3(hdl_name_override: Optional[str] = None)[source]

Bases: SimpleComentedUnit2

dynamically generated, for example loaded from file or builded from unit content

hwtLib.examples.parametrization module

class hwtLib.examples.parametrization.ParametrizationExample(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

HDL params

  • PARAM_0 - default value 0 of type int

  • PARAM_10 - default value 10 of type int

  • PARAM_1_sll_512 - default value <BitsVal 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096> of type <Bits, 513bits>

  • PARAM_1_sll_512_py_int - default value 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096 of type int

HDL IO
schematic

hwtLib.examples.showcase0 module

The class Showcase0 can be converted to various target formats as can be seen in “main” of this file.

There are several examples:

Verilog Std IEEE 1364-2001
  1//
  2//    Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
  3//
  4//    .. hwt-autodoc::
  5//    
  6module Showcase0 (
  7    input wire[31:0] a,
  8    input wire signed[31:0] b,
  9    output reg[31:0] c,
 10    input wire clk,
 11    output reg cmp_0,
 12    output reg cmp_1,
 13    output reg cmp_2,
 14    output reg cmp_3,
 15    output reg cmp_4,
 16    output reg cmp_5,
 17    output reg[31:0] contOut,
 18    input wire[31:0] d,
 19    input wire e,
 20    output wire f,
 21    output reg[15:0] fitted,
 22    output reg[7:0] g,
 23    output reg[7:0] h,
 24    input wire[1:0] i,
 25    output reg[7:0] j,
 26    output reg[31:0] k,
 27    output wire out,
 28    output wire output_0,
 29    input wire rst_n,
 30    output reg[7:0] sc_signal
 31);
 32    localparam [31:0] const_private_signal = 32'h0000007b;
 33    reg signed[7:0] fallingEdgeRam[0:3];
 34    reg r = 1'b0;
 35    reg[1:0] r_0 = 2'b00;
 36    reg[1:0] r_1 = 2'b00;
 37    reg r_next;
 38    wire[1:0] r_next_0;
 39    wire[1:0] r_next_1;
 40    reg[7:0] rom[0:3];
 41    always @(a, b) begin: assig_process_c
 42        c = a + $signed(b);
 43    end
 44
 45    always @(a) begin: assig_process_cmp_0
 46        cmp_0 = a < 32'h00000004;
 47    end
 48
 49    always @(a) begin: assig_process_cmp_1
 50        cmp_1 = a > 32'h00000004;
 51    end
 52
 53    always @(b) begin: assig_process_cmp_2
 54        cmp_2 = b <= $signed(32'h00000004);
 55    end
 56
 57    always @(b) begin: assig_process_cmp_3
 58        cmp_3 = b >= $signed(32'h00000004);
 59    end
 60
 61    always @(b) begin: assig_process_cmp_4
 62        cmp_4 = b != $signed(32'h00000004);
 63    end
 64
 65    always @(b) begin: assig_process_cmp_5
 66        cmp_5 = b == $signed(32'h00000004);
 67    end
 68
 69    always @(*) begin: assig_process_contOut
 70        contOut = const_private_signal;
 71    end
 72
 73    assign f = r;
 74    always @(negedge clk) begin: assig_process_fallingEdgeRam
 75        fallingEdgeRam[r_1] <= $unsigned(a[7:0]);
 76        k <= {24'h000000, $signed(fallingEdgeRam[r_1])};
 77    end
 78
 79    always @(a) begin: assig_process_fitted
 80        fitted = a[15:0];
 81    end
 82
 83    always @(a, b) begin: assig_process_g
 84        g = {{a[1] & b[1], a[0] ^ b[0] | a[1]}, a[5:0]};
 85    end
 86
 87    always @(a, r) begin: assig_process_h
 88        if (a[2])
 89            if (r)
 90                h = 8'h00;
 91            else if (a[1])
 92                h = 8'h01;
 93            else
 94                h = 8'h02;
 95    end
 96
 97    always @(posedge clk) begin: assig_process_j
 98        j <= rom[r_1];
 99    end
100
101    assign out = 1'b0;
102    assign output_0 = 1'bx;
103    always @(posedge clk) begin: assig_process_r
104        if (rst_n == 1'b0) begin
105            r_1 <= 2'b00;
106            r_0 <= 2'b00;
107            r <= 1'b0;
108        end else begin
109            r_1 <= r_next_1;
110            r_0 <= r_next_0;
111            r <= r_next;
112        end
113    end
114
115    assign r_next_0 = i;
116    assign r_next_1 = r_0;
117    always @(e, r) begin: assig_process_r_next_1
118        if (~r)
119            r_next = e;
120        else
121            r_next = r;
122    end
123
124    always @(a) begin: assig_process_sc_signal
125        case(a)
126            32'h00000001:
127                sc_signal = 8'h00;
128            32'h00000002:
129                sc_signal = 8'h01;
130            32'h00000003:
131                sc_signal = 8'h03;
132            default:
133                sc_signal = 8'h04;
134        endcase
135    end
136
137    initial begin
138        rom[0] = 0;
139        rom[1] = 1;
140        rom[2] = 2;
141        rom[3] = 3;
142    end
143
144endmodule
VHDL IEEE Std 1076-2002
  1LIBRARY IEEE;
  2USE IEEE.std_logic_1164.ALL;
  3USE IEEE.numeric_std.ALL;
  4--
  5--    Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
  6--
  7--    .. hwt-autodoc::
  8--    
  9ENTITY Showcase0 IS
 10    PORT(
 11        a : IN UNSIGNED(31 DOWNTO 0);
 12        b : IN SIGNED(31 DOWNTO 0);
 13        c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 14        clk : IN STD_LOGIC;
 15        cmp_0 : OUT STD_LOGIC;
 16        cmp_1 : OUT STD_LOGIC;
 17        cmp_2 : OUT STD_LOGIC;
 18        cmp_3 : OUT STD_LOGIC;
 19        cmp_4 : OUT STD_LOGIC;
 20        cmp_5 : OUT STD_LOGIC;
 21        contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 22        d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 23        e : IN STD_LOGIC;
 24        f : OUT STD_LOGIC;
 25        fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
 26        g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 27        h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 28        i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
 29        j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 30        k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 31        out_0 : OUT STD_LOGIC;
 32        output : OUT STD_LOGIC;
 33        rst_n : IN STD_LOGIC;
 34        sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
 35    );
 36END ENTITY;
 37
 38ARCHITECTURE rtl OF Showcase0 IS
 39    TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
 40    TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
 41    CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
 42    SIGNAL fallingEdgeRam : arr_t_0;
 43    SIGNAL r : STD_LOGIC := '0';
 44    SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
 45    SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
 46    SIGNAL r_next : STD_LOGIC;
 47    SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
 48    SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
 49    CONSTANT rom : arr_t_1 := (
 50        UNSIGNED'(X"00"),
 51        UNSIGNED'(X"01"),
 52        UNSIGNED'(X"02"),
 53        UNSIGNED'(X"03"));
 54BEGIN
 55    assig_process_c: PROCESS(a, b)
 56        VARIABLE tmpCastExpr_0 : UNSIGNED(31 DOWNTO 0);
 57    BEGIN
 58        tmpCastExpr_0 := a + UNSIGNED(b);
 59        c <= STD_LOGIC_VECTOR(tmpCastExpr_0);
 60    END PROCESS;
 61    cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
 62    cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
 63    cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
 64    cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
 65    cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
 66    cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
 67    contOut <= STD_LOGIC_VECTOR(const_private_signal);
 68    f <= r;
 69    assig_process_fallingEdgeRam: PROCESS(clk)
 70        VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
 71        VARIABLE tmpCastExpr_2 : SIGNED(7 DOWNTO 0);
 72        VARIABLE tmpCastExpr_1 : UNSIGNED(7 DOWNTO 0);
 73    BEGIN
 74        tmpCastExpr_0 := a(7 DOWNTO 0);
 75        tmpCastExpr_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
 76        tmpCastExpr_1 := UNSIGNED(tmpCastExpr_2);
 77        IF FALLING_EDGE(clk) THEN
 78            fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpCastExpr_0);
 79            k <= X"000000" & STD_LOGIC_VECTOR(tmpCastExpr_1);
 80        END IF;
 81    END PROCESS;
 82    assig_process_fitted: PROCESS(a)
 83        VARIABLE tmpCastExpr_0 : UNSIGNED(15 DOWNTO 0);
 84    BEGIN
 85        tmpCastExpr_0 := a(15 DOWNTO 0);
 86        fitted <= STD_LOGIC_VECTOR(tmpCastExpr_0);
 87    END PROCESS;
 88    assig_process_g: PROCESS(a, b)
 89        VARIABLE tmpCastExpr_0 : UNSIGNED(5 DOWNTO 0);
 90    BEGIN
 91        tmpCastExpr_0 := a(5 DOWNTO 0);
 92        g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpCastExpr_0);
 93    END PROCESS;
 94    assig_process_h: PROCESS(a, r)
 95    BEGIN
 96        IF a(2) = '1' THEN
 97            IF r = '1' THEN
 98                h <= X"00";
 99            ELSIF a(1) = '1' THEN
100                h <= X"01";
101            ELSE
102                h <= X"02";
103            END IF;
104        END IF;
105    END PROCESS;
106    assig_process_j: PROCESS(clk)
107        VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
108    BEGIN
109        tmpCastExpr_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
110        IF RISING_EDGE(clk) THEN
111            j <= STD_LOGIC_VECTOR(tmpCastExpr_0);
112        END IF;
113    END PROCESS;
114    out_0 <= '0';
115    output <= 'X';
116    assig_process_r: PROCESS(clk)
117    BEGIN
118        IF RISING_EDGE(clk) THEN
119            IF rst_n = '0' THEN
120                r_1 <= "00";
121                r_0 <= "00";
122                r <= '0';
123            ELSE
124                r_1 <= r_next_1;
125                r_0 <= r_next_0;
126                r <= r_next;
127            END IF;
128        END IF;
129    END PROCESS;
130    r_next_0 <= i;
131    r_next_1 <= r_0;
132    assig_process_r_next_1: PROCESS(e, r)
133    BEGIN
134        IF NOT r = '1' THEN
135            r_next <= e;
136        ELSE
137            r_next <= r;
138        END IF;
139    END PROCESS;
140    assig_process_sc_signal: PROCESS(a)
141    BEGIN
142        CASE a IS
143            WHEN UNSIGNED'(X"00000001") =>
144                sc_signal <= X"00";
145            WHEN UNSIGNED'(X"00000002") =>
146                sc_signal <= X"01";
147            WHEN UNSIGNED'(X"00000003") =>
148                sc_signal <= X"03";
149            WHEN OTHERS =>
150                sc_signal <= X"04";
151        END CASE;
152    END PROCESS;
153END ARCHITECTURE;
SystemC IEEE Std 1666-2011
  1#include <systemc.h>
  2
  3//
  4//    Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
  5//
  6//    .. hwt-autodoc::
  7//    
  8SC_MODULE(Showcase0) {
  9    // ports
 10    sc_in<sc_uint<32>> a;
 11    sc_in<sc_int<32>> b;
 12    sc_out<sc_uint<32>> c;
 13    sc_in_clk clk;
 14    sc_out<sc_uint<1>> cmp_0;
 15    sc_out<sc_uint<1>> cmp_1;
 16    sc_out<sc_uint<1>> cmp_2;
 17    sc_out<sc_uint<1>> cmp_3;
 18    sc_out<sc_uint<1>> cmp_4;
 19    sc_out<sc_uint<1>> cmp_5;
 20    sc_out<sc_uint<32>> contOut;
 21    sc_in<sc_uint<32>> d;
 22    sc_in<sc_uint<1>> e;
 23    sc_out<sc_uint<1>> f;
 24    sc_out<sc_uint<16>> fitted;
 25    sc_out<sc_uint<8>> g;
 26    sc_out<sc_uint<8>> h;
 27    sc_in<sc_uint<2>> i;
 28    sc_out<sc_uint<8>> j;
 29    sc_out<sc_uint<32>> k;
 30    sc_out<sc_uint<1>> out;
 31    sc_out<sc_uint<1>> output;
 32    sc_in<sc_uint<1>> rst_n;
 33    sc_out<sc_uint<8>> sc_signal_0;
 34    // component instances
 35    // internal signals
 36    sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
 37    sc_int<8> fallingEdgeRam[4];
 38    sc_uint<1> r = sc_uint<1>("0b0");
 39    sc_uint<2> r_0 = sc_uint<2>("0b00");
 40    sc_uint<2> r_1 = sc_uint<2>("0b00");
 41    sc_signal<sc_uint<1>> r_next;
 42    sc_signal<sc_uint<2>> r_next_0;
 43    sc_signal<sc_uint<2>> r_next_1;
 44    sc_uint<8> rom[4] = {sc_uint<8>("0x00"), 
 45        sc_uint<8>("0x01"), 
 46        sc_uint<8>("0x02"), 
 47        sc_uint<8>("0x03"), 
 48        };
 49    void assig_process_c() {
 50        c.write(static_cast<sc_uint<32>>(a.read() + static_cast<sc_uint<32>>(b.read())));
 51    }
 52
 53    void assig_process_cmp_0() {
 54        cmp_0.write(a.read() < sc_uint<32>("0x00000004"));
 55    }
 56
 57    void assig_process_cmp_1() {
 58        cmp_1.write(a.read() > sc_uint<32>("0x00000004"));
 59    }
 60
 61    void assig_process_cmp_2() {
 62        cmp_2.write(b.read() <= sc_int<32>("0x00000004"));
 63    }
 64
 65    void assig_process_cmp_3() {
 66        cmp_3.write(b.read() >= sc_int<32>("0x00000004"));
 67    }
 68
 69    void assig_process_cmp_4() {
 70        cmp_4.write(b.read() != sc_int<32>("0x00000004"));
 71    }
 72
 73    void assig_process_cmp_5() {
 74        cmp_5.write(b.read() == sc_int<32>("0x00000004"));
 75    }
 76
 77    void assig_process_contOut() {
 78        contOut.write(static_cast<sc_uint<32>>(const_private_signal));
 79    }
 80
 81    void assig_process_f() {
 82        f.write(r);
 83    }
 84
 85    void assig_process_fallingEdgeRam() {
 86        sc_signal<sc_uint<32>> tmpConcat_0;
 87        tmpConcat_0.write((sc_uint<24>("0x000000"), static_cast<sc_uint<8>>(static_cast<sc_uint<8>>(fallingEdgeRam[r_1])), ));
 88        {
 89            (fallingEdgeRam[r_1]).write(static_cast<sc_int<8>>(a.read().range(sc_int<32>("0x00000008"), sc_int<32>("0x00000000"))));
 90            k = tmpConcat_0.read();
 91        }
 92    }
 93
 94    void assig_process_fitted() {
 95        fitted.write(static_cast<sc_uint<16>>(a.read().range(sc_int<32>("0x00000010"), sc_int<32>("0x00000000"))));
 96    }
 97
 98    void assig_process_g() {
 99        sc_signal<sc_uint<2>> tmpConcat_1;
100        sc_signal<sc_uint<8>> tmpConcat_0;
101        tmpConcat_1.write((a.read()[sc_int<32>("0x00000001")] & b.read()[sc_int<32>("0x00000001")], a.read()[sc_int<32>("0x00000000")] ^ b.read()[sc_int<32>("0x00000000")] | a.read()[sc_int<32>("0x00000001")], ));
102        tmpConcat_0.write((tmpConcat_1.read(), static_cast<sc_uint<6>>(a.read().range(sc_int<32>("0x00000006"), sc_int<32>("0x00000000"))), ));
103        g.write(tmpConcat_0.read());
104    }
105
106    void assig_process_h() {
107        if (a.read()[sc_int<32>("0x00000002")] == sc_uint<1>("0b1"))
108            if (r == sc_uint<1>("0b1"))
109                h.write(sc_uint<8>("0x00"));
110            else if (a.read()[sc_int<32>("0x00000001")] == sc_uint<1>("0b1"))
111                h.write(sc_uint<8>("0x01"));
112            else
113                h.write(sc_uint<8>("0x02"));
114    }
115
116    void assig_process_j() {
117        j = static_cast<sc_uint<8>>(rom[r_1]);
118    }
119
120    void assig_process_out() {
121        out.write(sc_uint<1>("0b0"));
122    }
123
124    void assig_process_output() {
125        output.write(sc_uint<1>("0bX"));
126    }
127
128    void assig_process_r() {
129        if (rst_n.read() == sc_uint<1>("0b0")) {
130            r_1 = sc_uint<2>("0b00");
131            r_0 = sc_uint<2>("0b00");
132            r = sc_uint<1>("0b0");
133        } else {
134            r_1 = r_next_1.read();
135            r_0 = r_next_0.read();
136            r = r_next.read();
137        }
138    }
139
140    void assig_process_r_next() {
141        r_next_0.write(i.read());
142    }
143
144    void assig_process_r_next_0() {
145        r_next_1.write(r_0);
146    }
147
148    void assig_process_r_next_1() {
149        if (r == sc_uint<1>("0b0"))
150            r_next.write(e.read());
151        else
152            r_next.write(r);
153    }
154
155    void assig_process_sc_signal_0() {
156        switch(a.read()) {
157        case sc_uint<32>("0x00000001"): {
158                sc_signal_0.write(sc_uint<8>("0x00"));
159                break;
160            }
161        case sc_uint<32>("0x00000002"): {
162                sc_signal_0.write(sc_uint<8>("0x01"));
163                break;
164            }
165        case sc_uint<32>("0x00000003"): {
166                sc_signal_0.write(sc_uint<8>("0x03"));
167                break;
168            }
169        default:
170                sc_signal_0.write(sc_uint<8>("0x04"));
171        }
172    }
173
174    SC_CTOR(Showcase0) {
175        SC_METHOD(assig_process_c);
176        sensitive << a << b;
177        SC_METHOD(assig_process_cmp_0);
178        sensitive << a;
179        SC_METHOD(assig_process_cmp_1);
180        sensitive << a;
181        SC_METHOD(assig_process_cmp_2);
182        sensitive << b;
183        SC_METHOD(assig_process_cmp_3);
184        sensitive << b;
185        SC_METHOD(assig_process_cmp_4);
186        sensitive << b;
187        SC_METHOD(assig_process_cmp_5);
188        sensitive << b;
189        assig_process_contOut();
190        SC_METHOD(assig_process_f);
191        sensitive << r;
192        SC_METHOD(assig_process_fallingEdgeRam);
193        sensitive << clk.neg();
194        SC_METHOD(assig_process_fitted);
195        sensitive << a;
196        SC_METHOD(assig_process_g);
197        sensitive << a << b;
198        SC_METHOD(assig_process_h);
199        sensitive << a << r;
200        SC_METHOD(assig_process_j);
201        sensitive << clk.pos();
202        assig_process_out();
203        assig_process_output();
204        SC_METHOD(assig_process_r);
205        sensitive << clk.pos();
206        SC_METHOD(assig_process_r_next);
207        sensitive << i;
208        SC_METHOD(assig_process_r_next_0);
209        sensitive << r_0;
210        SC_METHOD(assig_process_r_next_1);
211        sensitive << e << r;
212        SC_METHOD(assig_process_sc_signal_0);
213        sensitive << a;
214        // connect ports
215    }
216};
HWT hwt.synthesizer.unit.Unit class definition
  1from hwt.code import If, Switch, Concat
  2from hwt.code_utils import rename_signal
  3from hwt.hdl.types.array import HArray
  4from hwt.hdl.types.bits import Bits
  5from hwt.hdl.types.defs import INT, SLICE, STR, BIT, FLOAT64
  6from hwt.hdl.types.enum import HEnum
  7from hwt.interfaces.std import Signal
  8from hwt.synthesizer.param import Param
  9from hwt.synthesizer.unit import Unit
 10
 11class Showcase0(Unit):
 12    """
 13        Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
 14    
 15        .. hwt-autodoc::
 16        
 17    """
 18    def _declr(self):
 19        # ports
 20        self.a = Signal(Bits(32, signed=False))
 21        self.b = Signal(Bits(32, signed=True))
 22        self.c = Signal(Bits(32))._m()
 23        self.clk = Signal(Bits(1))
 24        self.cmp_0 = Signal(Bits(1))._m()
 25        self.cmp_1 = Signal(Bits(1))._m()
 26        self.cmp_2 = Signal(Bits(1))._m()
 27        self.cmp_3 = Signal(Bits(1))._m()
 28        self.cmp_4 = Signal(Bits(1))._m()
 29        self.cmp_5 = Signal(Bits(1))._m()
 30        self.contOut = Signal(Bits(32))._m()
 31        self.d = Signal(Bits(32))
 32        self.e = Signal(Bits(1))
 33        self.f = Signal(Bits(1))._m()
 34        self.fitted = Signal(Bits(16))._m()
 35        self.g = Signal(Bits(8))._m()
 36        self.h = Signal(Bits(8))._m()
 37        self.i = Signal(Bits(2))
 38        self.j = Signal(Bits(8))._m()
 39        self.k = Signal(Bits(32))._m()
 40        self.out = Signal(Bits(1))._m()
 41        self.output = Signal(Bits(1))._m()
 42        self.rst_n = Signal(Bits(1, negated=True))
 43        self.sc_signal = Signal(Bits(8))._m()
 44        # component instances
 45
 46    def _impl(self):
 47        a, b, c, clk, cmp_0, cmp_1, cmp_2, cmp_3, cmp_4, cmp_5, contOut, \
 48        d, e, f, fitted, g, h, i, j, k, out, \
 49        output, rst_n, sc_signal = \
 50        self.a, self.b, self.c, self.clk, self.cmp_0, self.cmp_1, self.cmp_2, self.cmp_3, self.cmp_4, self.cmp_5, self.contOut, \
 51        self.d, self.e, self.f, self.fitted, self.g, self.h, self.i, self.j, self.k, self.out, \
 52        self.output, self.rst_n, self.sc_signal
 53        # internal signals
 54        const_private_signal = Bits(32, signed=False).from_py(123)
 55        fallingEdgeRam = self._sig("fallingEdgeRam", Bits(8, signed=True)[4], def_val=None)
 56        r = self._sig("r", Bits(1), def_val=0)
 57        r_0 = self._sig("r_0", Bits(2), def_val=0)
 58        r_1 = self._sig("r_1", Bits(2), def_val=0)
 59        r_next = self._sig("r_next", Bits(1), def_val=None)
 60        r_next_0 = self._sig("r_next_0", Bits(2), def_val=None)
 61        r_next_1 = self._sig("r_next_1", Bits(2), def_val=None)
 62        rom = Bits(8, signed=False)[4].from_py({0: 0,
 63            1: 1,
 64            2: 2,
 65            3: 3
 66        })
 67        # assig_process_c
 68        c((a + b._reinterpret_cast(Bits(32, signed=False)))._reinterpret_cast(Bits(32)))
 69        # assig_process_cmp_0
 70        cmp_0(a < 4)
 71        # assig_process_cmp_1
 72        cmp_1(a > 4)
 73        # assig_process_cmp_2
 74        cmp_2(b <= 4)
 75        # assig_process_cmp_3
 76        cmp_3(b >= 4)
 77        # assig_process_cmp_4
 78        cmp_4(b != 4)
 79        # assig_process_cmp_5
 80        cmp_5(b._eq(4))
 81        # assig_process_contOut
 82        contOut(const_private_signal._reinterpret_cast(Bits(32)))
 83        # assig_process_f
 84        f(r)
 85        # assig_process_fallingEdgeRam
 86        If(clk._onFallingEdge(),
 87            fallingEdgeRam[r_1](a[8:0]._reinterpret_cast(Bits(8, signed=True))),
 88            k(Concat(Bits(24).from_py(0), fallingEdgeRam[r_1]._reinterpret_cast(Bits(8, signed=False))._reinterpret_cast(Bits(8))))
 89        )
 90        # assig_process_fitted
 91        fitted(a[16:0]._reinterpret_cast(Bits(16)))
 92        # assig_process_g
 93        g(Concat(Concat(a[1] & b[1], a[0] ^ b[0] | a[1]), a[6:0]._reinterpret_cast(Bits(6))))
 94        # assig_process_h
 95        If(a[2]._eq(1),
 96            If(r._eq(1),
 97                h(0)
 98            ).Elif(a[1]._eq(1),
 99                h(1)
100            ).Else(
101                h(2)
102            )
103        )
104        # assig_process_j
105        If(clk._onRisingEdge(),
106            j(rom[r_1]._reinterpret_cast(Bits(8)))
107        )
108        # assig_process_out
109        out(0)
110        # assig_process_output
111        output(None)
112        # assig_process_r
113        If(clk._onRisingEdge(),
114            If(rst_n._eq(0),
115                r_1(0),
116                r_0(0),
117                r(0)
118            ).Else(
119                r_1(r_next_1),
120                r_0(r_next_0),
121                r(r_next)
122            )
123        )
124        # assig_process_r_next
125        r_next_0(i)
126        # assig_process_r_next_0
127        r_next_1(r_0)
128        # assig_process_r_next_1
129        If(r._eq(0),
130            r_next(e)
131        ).Else(
132            r_next(r)
133        )
134        # assig_process_sc_signal
135        Switch(a)\
136            .Case(1,
137                sc_signal(0))\
138            .Case(2,
139                sc_signal(1))\
140            .Case(3,
141                sc_signal(3))\
142            .Default(
143                sc_signal(4))
class hwtLib.examples.showcase0.Showcase0[source]

Bases: Unit

Every HW component class has to be derived from hwt.synthesizer.unit.Unit class

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__init__()[source]
_declr()[source]

In this function collecting of public interfaces is performed on every attribute assignment. Instances of Interface or hwt.synthesizer.unit.Unit are recognized by hwt.synthesizer.unit.Unit instance and are used as public interface of this unit.

Master interfaces are marked by “._m()”, meaning of master direction is specified in interface class. For simple signal master direction means output.

_impl()[source]

Purpose of this method In this method all public interfaces and configuration has been made and they can not be edited.

hwtLib.examples.showcase0.foo(condition0, statements, condition1, fallback0, fallback1)[source]

Python functions used as macro

hwtLib.examples.simple module

class hwtLib.examples.simple.SimpleUnit(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

In order to create a new unit you have to make new class derived from Unit.

You can use sphinx-hwt plugin for sphinx document generator to generate interactive schematic and documentation. Schematic is generated by directive bellow.

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_declr()[source]

_declr() is like header of Unit. There you have to declare things which should be visible from outside.

_impl()[source]

_impl() is like body of unit. Logic and connections are specified i`qn this function.

hwtLib.examples.simple2withNonDirectIntConnection module

class hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnection(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

HDL params

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

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class hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnectionTC(methodName='runTest')[source]

Bases: SimTestCase

classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_passData()[source]

hwtLib.examples.simpleAxiStream module

class hwtLib.examples.simpleAxiStream.SimpleUnitAxiStream(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

Example of unit with axi stream interface

HDL params

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

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hwtLib.examples.simpleWithNonDirectIntConncetion module

class hwtLib.examples.simpleWithNonDirectIntConncetion.SimpleWithNonDirectIntConncetion(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

Example of fact that interfaces does not have to be only extern the can be used even for connection inside unit

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class hwtLib.examples.simpleWithNonDirectIntConncetion.SimpleWithNonDirectIntConncetionTC(methodName='runTest')[source]

Bases: SimTestCase

classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_passData()[source]

hwtLib.examples.simpleWithParam module

class hwtLib.examples.simpleWithParam.SimpleUnitWithParam(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

Simple parametrized unit.

HDL params

  • DATA_WIDTH - default value 8 of type int

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class hwtLib.examples.simpleWithParam.SimpleUnitWithParamTC(methodName='runTest')[source]

Bases: SimTestCase

classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_simple()[source]

hwtLib.examples.simple_ip module

hwtLib.examples.timers module

class hwtLib.examples.timers.DynamicCounterInstancesExample(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

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class hwtLib.examples.timers.TimerInfoTest(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

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class hwtLib.examples.timers.TimerTC(methodName='runTest')[source]

Bases: SimTestCase

tearDown()[source]

Hook method for deconstructing the test fixture after testing it.

test_basic()[source]
test_dynamic_simple()[source]
class hwtLib.examples.timers.TimerTestUnit(hdl_name_override: Optional[str] = None)[source]

Bases: Unit

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