hwtLib.examples package

This module is a collection of examples. Examples usually do have 2 purposes. First is to demostrate the functionality. Second is to test it.

Subpackages

Submodules

hwtLib.examples.base_serialization_TC module

class hwtLib.examples.base_serialization_TC.BaseSerializationTC(methodName='runTest')[source]

Bases: unittest.case.TestCase

SERIALIZER_BY_EXT = {'cpp': <class 'hwt.serializer.systemC.SystemCSerializer'>, 'py': <class 'hwt.serializer.hwt.HwtSerializer'>, 'v': <class 'hwt.serializer.verilog.VerilogSerializer'>, 'vhd': <class 'hwt.serializer.vhdl.Vhdl2008Serializer'>}
assert_same_as_file(s, file_name: str)[source]
assert_serializes_as_file(u: hwt.synthesizer.unit.Unit, file_name: str)[source]
strStructureCmp(cont, tmpl)[source]

hwtLib.examples.emptyUnitWithSpi module

class hwtLib.examples.emptyUnitWithSpi.EmptyUnitWithSpi[source]

Bases: hwt.synthesizer.interfaceLevel.emptyUnit.EmptyUnit

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

class hwtLib.examples.emptyUnitWithSpi.EmptyUnitWithSpiTC(methodName='runTest')[source]

Bases: hwtLib.examples.base_serialization_TC.BaseSerializationTC

test_vhdl()[source]

hwtLib.examples.hdlComments module

class hwtLib.examples.hdlComments.SimpleComentedUnit[source]

Bases: hwt.synthesizer.unit.Unit

This is comment for SimpleComentedUnit entity, it will be rendered before entity as comment. Do not forget that class inheritance does apply for docstring as well.

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.hdlComments.SimpleComentedUnit2[source]

Bases: hwtLib.examples.hdlComments.SimpleComentedUnit

single line

class hwtLib.examples.hdlComments.SimpleComentedUnit3[source]

Bases: hwtLib.examples.hdlComments.SimpleComentedUnit2

dynamically generated, for example loaded from file or builded from unit content

hwtLib.examples.parametrization module

class hwtLib.examples.parametrization.ParametrizationExample[source]

Bases: hwt.synthesizer.unit.Unit

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.examples.showcase0 module

The class Showcase0 can be converted to various target formats as can be seen in “main” of this file.

There are several examples:

Verilog Std IEEE 1364-2001
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//
//    Every HW component class has to be derived from Unit class
//
//    .. hwt-schematic::
//    
module Showcase0 (
    input  unsigned[31:0] a,
    input  signed[31:0] b,
    output reg[31:0] c,
    input  clk,
    output reg cmp_0,
    output reg cmp_1,
    output reg cmp_2,
    output reg cmp_3,
    output reg cmp_4,
    output reg cmp_5,
    output reg[31:0] contOut,
    input [31:0] d,
    input  e,
    output  f,
    output reg[15:0] fitted,
    output reg[7:0] g,
    output reg[7:0] h,
    input [1:0] i,
    output reg[7:0] j,
    output reg[31:0] k,
    output  out,
    output  output_0,
    input  rst_n,
    output reg[7:0] sc_signal
);
    localparam reg unsigned[31:0] const_private_signal = 32'h0000007b;
    reg signed[7:0] fallingEdgeRam[0:3];
    reg r = 1'b0;
    reg[1:0] r_0 = 2'b00;
    reg[1:0] r_1 = 2'b00;
    reg r_next = 1'bx;
    wire[1:0] r_next_0 = 2'bxx;
    wire[1:0] r_next_1 = 2'bxx;
    reg unsigned[7:0] rom[0:3];
    always @(a, b) begin: assig_process_c
        c = a + $signed(b);
    end

    always @(a) begin: assig_process_cmp_0
        cmp_0 = a < 32'h00000004;
    end

    always @(a) begin: assig_process_cmp_1
        cmp_1 = a > 32'h00000004;
    end

    always @(b) begin: assig_process_cmp_2
        cmp_2 = b <= $signed(32'h00000004);
    end

    always @(b) begin: assig_process_cmp_3
        cmp_3 = b >= $signed(32'h00000004);
    end

    always @(b) begin: assig_process_cmp_4
        cmp_4 = b != $signed(32'h00000004);
    end

    always @(b) begin: assig_process_cmp_5
        cmp_5 = b == $signed(32'h00000004);
    end

    always @(*) begin: assig_process_contOut
        contOut = const_private_signal;
    end

    assign f = r;
    always @(negedge clk) begin: assig_process_fallingEdgeRam
        fallingEdgeRam[r_1] <= $unsigned(a[7:0]);
        k <= {24'h000000, $signed(fallingEdgeRam[r_1])};
    end

    always @(a) begin: assig_process_fitted
        fitted = a[15:0];
    end

    always @(a, b) begin: assig_process_g
        g = {{a[1] & b[1], a[0] ^ b[0] | a[1]}, a[5:0]};
    end

    always @(a, r) begin: assig_process_h
        if (a[2])
            if (r)
                h = 8'h00;
            else if (a[1])
                h = 8'h01;
            else
                h = 8'h02;
    end

    always @(posedge clk) begin: assig_process_j
        j <= rom[r_1];
    end

    assign out = 1'b0;
    assign output_0 = 1'bx;
    always @(posedge clk) begin: assig_process_r
        if (rst_n == 1'b0) begin
            r_1 <= 2'b00;
            r_0 <= 2'b00;
            r <= 1'b0;
        end else begin
            r_1 <= r_next_1;
            r_0 <= r_next_0;
            r <= r_next;
        end
    end

    assign r_next_0 = i;
    assign r_next_1 = r_0;
    always @(e, r) begin: assig_process_r_next_1
        if (~r)
            r_next = e;
        else
            r_next = r;
    end

    always @(a) begin: assig_process_sc_signal
        case(a)
            32'h00000001:
                sc_signal = 8'h00;
            32'h00000002:
                sc_signal = 8'h01;
            32'h00000003:
                sc_signal = 8'h03;
            default:
                sc_signal = 8'h04;
        endcase
    end

    initial begin
        rom[0] = 0;
        rom[1] = 1;
        rom[2] = 2;
        rom[3] = 3;
    end

endmodule
VHDL IEEE Std 1076-2002
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
--    Every HW component class has to be derived from Unit class
--
--    .. hwt-schematic::
--    
ENTITY Showcase0 IS
    PORT(
        a : IN UNSIGNED(31 DOWNTO 0);
        b : IN SIGNED(31 DOWNTO 0);
        c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        clk : IN STD_LOGIC;
        cmp_0 : OUT STD_LOGIC;
        cmp_1 : OUT STD_LOGIC;
        cmp_2 : OUT STD_LOGIC;
        cmp_3 : OUT STD_LOGIC;
        cmp_4 : OUT STD_LOGIC;
        cmp_5 : OUT STD_LOGIC;
        contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
        e : IN STD_LOGIC;
        f : OUT STD_LOGIC;
        fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
        k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
        out_0 : OUT STD_LOGIC;
        output : OUT STD_LOGIC;
        rst_n : IN STD_LOGIC;
        sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END ENTITY;

ARCHITECTURE rtl OF Showcase0 IS
    TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
    TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
    CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
    SIGNAL fallingEdgeRam : arr_t_0;
    SIGNAL r : STD_LOGIC := '0';
    SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
    SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
    SIGNAL r_next : STD_LOGIC;
    SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
    SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
    CONSTANT rom : arr_t_1 := (
        UNSIGNED'(X"00"),
        UNSIGNED'(X"01"),
        UNSIGNED'(X"02"),
        UNSIGNED'(X"03"));
BEGIN
    assig_process_c: PROCESS(a, b)
        VARIABLE tmpTypeConv_0 : UNSIGNED(31 DOWNTO 0);
    BEGIN
        tmpTypeConv_0 := a + UNSIGNED(b);
        c <= STD_LOGIC_VECTOR(tmpTypeConv_0);
    END PROCESS;
    cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
    cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
    cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
    cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
    cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
    cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
    contOut <= STD_LOGIC_VECTOR(const_private_signal);
    f <= r;
    assig_process_fallingEdgeRam: PROCESS(clk)
        VARIABLE tmpTypeConv_0 : UNSIGNED(7 DOWNTO 0);
        VARIABLE tmpTypeConv_1 : UNSIGNED(7 DOWNTO 0);
        VARIABLE tmpTypeConv_2 : SIGNED(7 DOWNTO 0);
    BEGIN
        tmpTypeConv_0 := a(7 DOWNTO 0);
        tmpTypeConv_1 := UNSIGNED(tmpTypeConv_2);
        tmpTypeConv_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
        IF FALLING_EDGE(clk) THEN
            fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpTypeConv_0);
            k <= X"000000" & STD_LOGIC_VECTOR(tmpTypeConv_1);
        END IF;
    END PROCESS;
    assig_process_fitted: PROCESS(a)
        VARIABLE tmpTypeConv_0 : UNSIGNED(15 DOWNTO 0);
    BEGIN
        tmpTypeConv_0 := a(15 DOWNTO 0);
        fitted <= STD_LOGIC_VECTOR(tmpTypeConv_0);
    END PROCESS;
    assig_process_g: PROCESS(a, b)
        VARIABLE tmpTypeConv_0 : UNSIGNED(5 DOWNTO 0);
    BEGIN
        tmpTypeConv_0 := a(5 DOWNTO 0);
        g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpTypeConv_0);
    END PROCESS;
    assig_process_h: PROCESS(a, r)
    BEGIN
        IF a(2) = '1' THEN
            IF r = '1' THEN
                h <= X"00";
            ELSIF a(1) = '1' THEN
                h <= X"01";
            ELSE
                h <= X"02";
            END IF;
        END IF;
    END PROCESS;
    assig_process_j: PROCESS(clk)
        VARIABLE tmpTypeConv_0 : UNSIGNED(7 DOWNTO 0);
    BEGIN
        tmpTypeConv_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
        IF RISING_EDGE(clk) THEN
            j <= STD_LOGIC_VECTOR(tmpTypeConv_0);
        END IF;
    END PROCESS;
    out_0 <= '0';
    output <= 'X';
    assig_process_r: PROCESS(clk)
    BEGIN
        IF RISING_EDGE(clk) THEN
            IF rst_n = '0' THEN
                r_1 <= "00";
                r_0 <= "00";
                r <= '0';
            ELSE
                r_1 <= r_next_1;
                r_0 <= r_next_0;
                r <= r_next;
            END IF;
        END IF;
    END PROCESS;
    r_next_0 <= i;
    r_next_1 <= r_0;
    assig_process_r_next_1: PROCESS(e, r)
    BEGIN
        IF NOT r = '1' THEN
            r_next <= e;
        ELSE
            r_next <= r;
        END IF;
    END PROCESS;
    assig_process_sc_signal: PROCESS(a)
    BEGIN
        CASE a IS
            WHEN UNSIGNED'(X"00000001") =>
                sc_signal <= X"00";
            WHEN UNSIGNED'(X"00000002") =>
                sc_signal <= X"01";
            WHEN UNSIGNED'(X"00000003") =>
                sc_signal <= X"03";
            WHEN OTHERS =>
                sc_signal <= X"04";
        END CASE;
    END PROCESS;
END ARCHITECTURE;
SystemC IEEE Std 1666-2011
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#include <systemc.h>

//
//    Every HW component class has to be derived from Unit class
//
//    .. hwt-schematic::
//    
SC_MODULE(Showcase0) {
    // ports
    sc_in<sc_uint<32>> a;
    sc_in<sc_int<32>> b;
    sc_out<sc_uint<32>> c;
    sc_in_clk clk;
    sc_out<sc_uint<1>> cmp_0;
    sc_out<sc_uint<1>> cmp_1;
    sc_out<sc_uint<1>> cmp_2;
    sc_out<sc_uint<1>> cmp_3;
    sc_out<sc_uint<1>> cmp_4;
    sc_out<sc_uint<1>> cmp_5;
    sc_out<sc_uint<32>> contOut;
    sc_in<sc_uint<32>> d;
    sc_in<sc_uint<1>> e;
    sc_out<sc_uint<1>> f;
    sc_out<sc_uint<16>> fitted;
    sc_out<sc_uint<8>> g;
    sc_out<sc_uint<8>> h;
    sc_in<sc_uint<2>> i;
    sc_out<sc_uint<8>> j;
    sc_out<sc_uint<32>> k;
    sc_out<sc_uint<1>> out;
    sc_out<sc_uint<1>> output;
    sc_in<sc_uint<1>> rst_n;
    sc_out<sc_uint<8>> sc_signal_0;
    // component instances
    // internal signals
    sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
    sc_int<8> fallingEdgeRam[4];
    sc_uint<1> r = sc_uint<1>("0b0");
    sc_uint<2> r_0 = sc_uint<2>("0b00");
    sc_uint<2> r_1 = sc_uint<2>("0b00");
    sc_signal<sc_uint<1>> r_next;
    sc_signal<sc_uint<2>> r_next_0;
    sc_signal<sc_uint<2>> r_next_1;
    sc_uint<8> rom[4] = {sc_uint<8>("0x00"), 
        sc_uint<8>("0x01"), 
        sc_uint<8>("0x02"), 
        sc_uint<8>("0x03"), 
        };
    void assig_process_c() {
        c.write(static_cast<sc_uint<32>>(a.read() + static_cast<sc_uint<32>>(b.read())));
    }

    void assig_process_cmp_0() {
        cmp_0.write(a.read() < sc_uint<32>("0x00000004"));
    }

    void assig_process_cmp_1() {
        cmp_1.write(a.read() > sc_uint<32>("0x00000004"));
    }

    void assig_process_cmp_2() {
        cmp_2.write(b.read() <= sc_int<32>("0x00000004"));
    }

    void assig_process_cmp_3() {
        cmp_3.write(b.read() >= sc_int<32>("0x00000004"));
    }

    void assig_process_cmp_4() {
        cmp_4.write(b.read() != sc_int<32>("0x00000004"));
    }

    void assig_process_cmp_5() {
        cmp_5.write(b.read() == sc_int<32>("0x00000004"));
    }

    void assig_process_contOut() {
        contOut.write(static_cast<sc_uint<32>>(const_private_signal));
    }

    void assig_process_f() {
        f.write(r);
    }

    void assig_process_fallingEdgeRam() {
        sc_signal<sc_uint<32>> tmpConcat_0;
        tmpConcat_0.write((sc_uint<24>("0x000000"), static_cast<sc_uint<8>>(static_cast<sc_uint<8>>(fallingEdgeRam[r_1])), ));
        {
            (fallingEdgeRam[r_1]).write(static_cast<sc_int<8>>(a.read().range(sc_int<32>("0x00000008"), sc_int<32>("0x00000000"))));
            k = tmpConcat_0.read();
        }
    }

    void assig_process_fitted() {
        fitted.write(static_cast<sc_uint<16>>(a.read().range(sc_int<32>("0x00000010"), sc_int<32>("0x00000000"))));
    }

    void assig_process_g() {
        sc_signal<sc_uint<8>> tmpConcat_0;
        sc_signal<sc_uint<2>> tmpConcat_1;
        tmpConcat_0.write((tmpConcat_1.read(), static_cast<sc_uint<6>>(a.read().range(sc_int<32>("0x00000006"), sc_int<32>("0x00000000"))), ));
        tmpConcat_1.write((a.read()[sc_int<32>("0x00000001")] & b.read()[sc_int<32>("0x00000001")], a.read()[sc_int<32>("0x00000000")] ^ b.read()[sc_int<32>("0x00000000")] | a.read()[sc_int<32>("0x00000001")], ));
        g.write(tmpConcat_0.read());
    }

    void assig_process_h() {
        if (a.read()[sc_int<32>("0x00000002")] == sc_uint<1>("0b1"))
            if (r == sc_uint<1>("0b1"))
                h.write(sc_uint<8>("0x00"));
            else if (a.read()[sc_int<32>("0x00000001")] == sc_uint<1>("0b1"))
                h.write(sc_uint<8>("0x01"));
            else
                h.write(sc_uint<8>("0x02"));
    }

    void assig_process_j() {
        j = static_cast<sc_uint<8>>(rom[r_1]);
    }

    void assig_process_out() {
        out.write(sc_uint<1>("0b0"));
    }

    void assig_process_output() {
        output.write(sc_uint<1>("0bX"));
    }

    void assig_process_r() {
        if (rst_n.read() == sc_uint<1>("0b0")) {
            r_1 = sc_uint<2>("0b00");
            r_0 = sc_uint<2>("0b00");
            r = sc_uint<1>("0b0");
        } else {
            r_1 = r_next_1.read();
            r_0 = r_next_0.read();
            r = r_next.read();
        }
    }

    void assig_process_r_next() {
        r_next_0.write(i.read());
    }

    void assig_process_r_next_0() {
        r_next_1.write(r_0);
    }

    void assig_process_r_next_1() {
        if (~r == sc_uint<1>("0b1"))
            r_next.write(e.read());
        else
            r_next.write(r);
    }

    void assig_process_sc_signal_0() {
        switch(a.read()) {
        case sc_uint<32>("0x00000001"): {
                sc_signal_0.write(sc_uint<8>("0x00"));
                break;
            }
        case sc_uint<32>("0x00000002"): {
                sc_signal_0.write(sc_uint<8>("0x01"));
                break;
            }
        case sc_uint<32>("0x00000003"): {
                sc_signal_0.write(sc_uint<8>("0x03"));
                break;
            }
        default:
                sc_signal_0.write(sc_uint<8>("0x04"));
        }
    }

    SC_CTOR(Showcase0) {
        SC_METHOD(assig_process_c);
        sensitive << a << b;
        SC_METHOD(assig_process_cmp_0);
        sensitive << a;
        SC_METHOD(assig_process_cmp_1);
        sensitive << a;
        SC_METHOD(assig_process_cmp_2);
        sensitive << b;
        SC_METHOD(assig_process_cmp_3);
        sensitive << b;
        SC_METHOD(assig_process_cmp_4);
        sensitive << b;
        SC_METHOD(assig_process_cmp_5);
        sensitive << b;
        assig_process_contOut();
        SC_METHOD(assig_process_f);
        sensitive << r;
        SC_METHOD(assig_process_fallingEdgeRam);
        sensitive << clk.neg();
        SC_METHOD(assig_process_fitted);
        sensitive << a;
        SC_METHOD(assig_process_g);
        sensitive << a << b;
        SC_METHOD(assig_process_h);
        sensitive << a << r;
        SC_METHOD(assig_process_j);
        sensitive << clk.pos();
        assig_process_out();
        assig_process_output();
        SC_METHOD(assig_process_r);
        sensitive << clk.pos();
        SC_METHOD(assig_process_r_next);
        sensitive << i;
        SC_METHOD(assig_process_r_next_0);
        sensitive << r_0;
        SC_METHOD(assig_process_r_next_1);
        sensitive << e << r;
        SC_METHOD(assig_process_sc_signal_0);
        sensitive << a;
        // connect ports
    }
};
HWT Unit class definition
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from hwt.code import power, If, Switch, Concat
from hwt.hdl.types.array import HArray
from hwt.hdl.types.bits import Bits
from hwt.hdl.types.defs import INT, SLICE
from hwt.hdl.types.enum import HEnum
from hwt.interfaces.std import Signal
from hwt.synthesizer.param import Param
from hwt.synthesizer.unit import Unit

class Showcase0(Unit):
    """
        Every HW component class has to be derived from Unit class
    
        .. hwt-schematic::
        
    """
    def _declr(self):
        # ports
        self.a = Signal(dtype=Bits(32, signed=False))
        self.b = Signal(dtype=Bits(32, signed=True))
        self.c = Signal(dtype=Bits(32))._m()
        self.clk = Signal(dtype=Bits(1))
        self.cmp_0 = Signal(dtype=Bits(1))._m()
        self.cmp_1 = Signal(dtype=Bits(1))._m()
        self.cmp_2 = Signal(dtype=Bits(1))._m()
        self.cmp_3 = Signal(dtype=Bits(1))._m()
        self.cmp_4 = Signal(dtype=Bits(1))._m()
        self.cmp_5 = Signal(dtype=Bits(1))._m()
        self.contOut = Signal(dtype=Bits(32))._m()
        self.d = Signal(dtype=Bits(32))
        self.e = Signal(dtype=Bits(1))
        self.f = Signal(dtype=Bits(1))._m()
        self.fitted = Signal(dtype=Bits(16))._m()
        self.g = Signal(dtype=Bits(8))._m()
        self.h = Signal(dtype=Bits(8))._m()
        self.i = Signal(dtype=Bits(2))
        self.j = Signal(dtype=Bits(8))._m()
        self.k = Signal(dtype=Bits(32))._m()
        self.out = Signal(dtype=Bits(1))._m()
        self.output = Signal(dtype=Bits(1))._m()
        self.rst_n = Signal(dtype=Bits(1, negated=True))
        self.sc_signal = Signal(dtype=Bits(8))._m()
        # component instances

    def _impl(self):
        # internal signals
        a, b, c, clk, cmp_0, cmp_1, cmp_2, cmp_3, cmp_4, cmp_5, contOut, d, e, f, fitted, g, h, i, j, k, out, output, rst_n, sc_signal = \
        self.a, self.b, self.c, self.clk, self.cmp_0, self.cmp_1, self.cmp_2, self.cmp_3, self.cmp_4, self.cmp_5, self.contOut, self.d, self.e, self.f, self.fitted, self.g, self.h, self.i, self.j, self.k, self.out, self.output, self.rst_n, self.sc_signal
        const_private_signal = self._sig("const_private_signal", Bits(32, signed=False), def_val=123)
        fallingEdgeRam = self._sig("fallingEdgeRam", Bits(8, signed=True)[4], def_val=None)
        r = self._sig("r", Bits(1), def_val=0)
        r_0 = self._sig("r_0", Bits(2), def_val=0)
        r_1 = self._sig("r_1", Bits(2), def_val=0)
        r_next = self._sig("r_next", Bits(1), def_val=None)
        r_next_0 = self._sig("r_next_0", Bits(2), def_val=None)
        r_next_1 = self._sig("r_next_1", Bits(2), def_val=None)
        rom = self._sig("rom", Bits(8, signed=False)[4], def_val={0: 0,
            1: 1,
            2: 2,
            3: 3
        })
        # assig_process_c
        c((a + b._reinterpret_cast(Bits(32, signed=False)))._reinterpret_cast(Bits(32)))
        # assig_process_cmp_0
        cmp_0(a < 4)
        # assig_process_cmp_1
        cmp_1(a > 4)
        # assig_process_cmp_2
        cmp_2(b <= 4)
        # assig_process_cmp_3
        cmp_3(b >= 4)
        # assig_process_cmp_4
        cmp_4(b != 4)
        # assig_process_cmp_5
        cmp_5(b._eq(4))
        # assig_process_contOut
        contOut(const_private_signal._reinterpret_cast(Bits(32)))
        # assig_process_f
        f(r)
        # assig_process_fallingEdgeRam
        If(clk._onFallingEdge(),
            fallingEdgeRam[r_1](a[8:0]._reinterpret_cast(Bits(8, signed=True))),
            k(Concat(Bits(24).from_py(0), fallingEdgeRam[r_1]._reinterpret_cast(Bits(8, signed=False))._reinterpret_cast(Bits(8))))
        )
        # assig_process_fitted
        fitted(a[16:0]._reinterpret_cast(Bits(16)))
        # assig_process_g
        g(Concat(Concat(a[1] & b[1], a[0] ^ b[0] | a[1]), a[6:0]._reinterpret_cast(Bits(6))))
        # assig_process_h
        If(a[2]._eq(1),
            If(r._eq(1),
                h(0)
            ).Elif(a[1]._eq(1),
                h(1)
            ).Else(
                h(2)
            )
        )
        # assig_process_j
        If(clk._onRisingEdge(),
            j(rom[r_1]._reinterpret_cast(Bits(8)))
        )
        # assig_process_out
        out(0)
        # assig_process_output
        output(None)
        # assig_process_r
        If(clk._onRisingEdge(),
            If(rst_n._eq(0),
                r_1(0),
                r_0(0),
                r(0)
            ).Else(
                r_1(r_next_1),
                r_0(r_next_0),
                r(r_next)
            )
        )
        # assig_process_r_next
        r_next_0(i)
        # assig_process_r_next_0
        r_next_1(r_0)
        # assig_process_r_next_1
        If((~r)._eq(1),
            r_next(e)
        ).Else(
            r_next(r)
        )
        # assig_process_sc_signal
        Switch(a)\
            .Case(1,
                sc_signal(0))\
            .Case(2,
                sc_signal(1))\
            .Case(3,
                sc_signal(3))\
            .Default(
                sc_signal(4))
class hwtLib.examples.showcase0.Showcase0[source]

Bases: hwt.synthesizer.unit.Unit

Every HW component class has to be derived from Unit class

schematic
__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

_declr()[source]

In this function collecting of public interfaces is performed on every attribute assignment. Instances of Interface or Unit are recognized by Unit instance and are used as public interface of this unit.

Master interfaces are marked by “._m()”, meaning of master direction is specified in interface class. For simple signal master direction means output.

_impl()[source]

Purpose of this method In this method all public interfaces and configuration has been made and they can not be edited.

hwtLib.examples.showcase0.foo(condition0, statements, condition1, fallback0, fallback1)[source]

Python functions used as macro

hwtLib.examples.simple module

class hwtLib.examples.simple.SimpleUnit[source]

Bases: hwt.synthesizer.unit.Unit

In order to create a new unit you have to make new class derived from Unit.

You can use sphinx-hwt plugin for sphinx document generator to generate interactive schematic and documentation. Schematic is generated by directive bellow.

schematic
_declr()[source]

_declr() is like header of Unit. There you have to declare things which should be visible from outside.

_impl()[source]

_impl() is like body of unit. Logic and connections are specified i`qn this function.

hwtLib.examples.simple2withNonDirectIntConnection module

class hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnection[source]

Bases: hwt.synthesizer.unit.Unit

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnectionTC(methodName='runTest')[source]

Bases: hwt.simulator.simTestCase.SingleUnitSimTestCase

classmethod getUnit() → hwt.synthesizer.unit.Unit[source]
test_passData()[source]

hwtLib.examples.simpleAxiStream module

class hwtLib.examples.simpleAxiStream.SimpleUnitAxiStream[source]

Bases: hwt.synthesizer.unit.Unit

Example of unit with axi stream interface

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.examples.simpleWithNonDirectIntConncetion module

class hwtLib.examples.simpleWithNonDirectIntConncetion.SimpleWithNonDirectIntConncetion[source]

Bases: hwt.synthesizer.unit.Unit

Example of fact that interfaces does not have to be only extern the can be used even for connection inside unit

schematic
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.simpleWithNonDirectIntConncetion.SimpleWithNonDirectIntConncetionTC(methodName='runTest')[source]

Bases: hwt.simulator.simTestCase.SingleUnitSimTestCase

classmethod getUnit() → hwt.synthesizer.unit.Unit[source]
test_passData()[source]

hwtLib.examples.simpleWithParam module

class hwtLib.examples.simpleWithParam.SimpleUnitWithParam[source]

Bases: hwt.synthesizer.unit.Unit

Simple parametrized unit.

schematic
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance

  • called in __init__ of class

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.simpleWithParam.SimpleUnitWithParamTC(methodName='runTest')[source]

Bases: hwt.simulator.simTestCase.SingleUnitSimTestCase

classmethod getUnit() → hwt.synthesizer.unit.Unit[source]
test_simple()[source]

hwtLib.examples.simple_ip module

class hwtLib.examples.simple_ip.SimpleUnit[source]

Bases: hwt.synthesizer.unit.Unit

_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

hwtLib.examples.timers module

class hwtLib.examples.timers.DynamicCounterInstancesExample[source]

Bases: hwt.synthesizer.unit.Unit

schematic
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.timers.TimerInfoTest[source]

Bases: hwt.synthesizer.unit.Unit

schematic
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr

class hwtLib.examples.timers.TimerTC(methodName='runTest')[source]

Bases: hwt.simulator.simTestCase.SimTestCase

test_basic()[source]
test_dynamic_simple()[source]
class hwtLib.examples.timers.TimerTestUnit[source]

Bases: hwt.synthesizer.unit.Unit

schematic
_declr()[source]

declarations

  • do all declarations of externally accessible objects there (Interfaces)

  • _declr method is called after _config

  • if this object is Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

_impl()[source]

implementations

  • implement functionality of componnent there

  • called after _declr