hwtLib.examples package

This module is a collection of examples. Examples usually do have 2 purposes. First is to demostrate the functionality. Second is to test it.

Subpackages

Submodules

hwtLib.examples.base_serialization_TC module

class hwtLib.examples.base_serialization_TC.BaseSerializationTC(methodName='runTest')[source]

Bases: SimTestCase

SERIALIZER_BY_EXT = {'cpp': <class 'hwt.serializer.systemC.SystemCSerializer'>, 'py': <class 'hwt.serializer.hwt.HwtSerializer'>, 'v': <class 'hwt.serializer.verilog.VerilogSerializer'>, 'vhd': <class 'hwt.serializer.vhdl.Vhdl2008Serializer'>}
__FILE__ = None
_classSetupFailed = False
_class_cleanups = []
static _runDifftoolCommand(oldFileName, newFileName)[source]
assert_same_as_file(s: str, file_name: str, printOnError=False, openDifftoolOnError=False)[source]
assert_serializes_as_file(m: HwModule, file_name: str)[source]
strStructureCmp(cont, tmpl: str)[source]
tearDown()[source]

Hook method for deconstructing the test fixture after testing it.

hwtLib.examples.emptyHwModuleWithSpi module

class hwtLib.examples.emptyHwModuleWithSpi.EmptyHwModuleWithSpi(hdlName: str | None = None)[source]

Bases: EmptyHwModule

__annotations__ = {}
class hwtLib.examples.emptyHwModuleWithSpi.EmptyHwModuleWithSpiTC(methodName='runTest')[source]

Bases: BaseSerializationTC

__FILE__ = '/home/docs/checkouts/readthedocs.org/user_builds/hwtlib/checkouts/latest/hwtLib/examples/emptyHwModuleWithSpi.py'
__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
test_vhdl()[source]

hwtLib.examples.hdlComments module

class hwtLib.examples.hdlComments.SimpleComentedHwModule(hdlName: str | None = None)[source]

Bases: HwModule

This is comment for SimpleComentedHwModule entity, it will be rendered before entity as comment. Do not forget that class inheritance does apply for docstring as well.

__annotations__ = {}
class hwtLib.examples.hdlComments.SimpleComentedHwModule2(hdlName: str | None = None)[source]

Bases: SimpleComentedHwModule

single line

__annotations__ = {}
class hwtLib.examples.hdlComments.SimpleComentedHwModule3(hdlName: str | None = None)[source]

Bases: SimpleComentedHwModule2

dynamically generated, for example loaded from file or builded from unit content

__annotations__ = {}

hwtLib.examples.parametrization module

class hwtLib.examples.parametrization.ParametrizationExample(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • PARAM_0 - default value 0 of type int

  • PARAM_10 - default value 10 of type int

  • PARAM_1_sll_512 - default value <HBitsConst b513 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096> of type <HBits, 513bits>

  • PARAM_1_sll_512_py_int - default value 13407807929942597099574024998205846127479365820592393377723561443721764030073546976801874298166903427690031858186486050853753882811946569946433649006084096 of type int

HDL IO:

  • din - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 10bits> - SLAVE

  • dout - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 20bits> - MASTER

schematic
__annotations__ = {}

hwtLib.examples.showcase0 module

The class Showcase0 can be converted to various target formats as can be seen in “main” of this file.

There are several examples:

Verilog Std IEEE 1364-2001
  1//
  2//Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
  3//
  4//.. hwt-autodoc::
  5module Showcase0 (
  6    input wire[31:0] a,
  7    input wire signed[31:0] b,
  8    output reg[31:0] c,
  9    input wire clk,
 10    output reg cmp_0,
 11    output reg cmp_1,
 12    output reg cmp_2,
 13    output reg cmp_3,
 14    output reg cmp_4,
 15    output reg cmp_5,
 16    output reg[31:0] contOut,
 17    input wire[31:0] d,
 18    input wire e,
 19    output wire f,
 20    output reg[15:0] fitted,
 21    output reg[7:0] g,
 22    output reg[7:0] h,
 23    input wire[1:0] i,
 24    output reg[7:0] j,
 25    output reg[31:0] k,
 26    output wire out,
 27    output wire output_0,
 28    input wire rst_n,
 29    output reg[7:0] sc_signal
 30);
 31    localparam [31:0] const_private_signal = 32'h0000007b;
 32    reg signed[7:0] fallingEdgeRam[0:3];
 33    reg r = 1'b0;
 34    reg[1:0] r_0 = 2'b00;
 35    reg[1:0] r_1 = 2'b00;
 36    reg r_next;
 37    wire[1:0] r_next_0;
 38    wire[1:0] r_next_1;
 39    reg[7:0] rom[0:3];
 40    always @(a, b) begin: assig_process_c
 41        c = a + $unsigned(b);
 42    end
 43
 44    always @(a) begin: assig_process_cmp_0
 45        cmp_0 = a < 32'h00000004;
 46    end
 47
 48    always @(a) begin: assig_process_cmp_1
 49        cmp_1 = a > 32'h00000004;
 50    end
 51
 52    always @(b) begin: assig_process_cmp_2
 53        cmp_2 = b <= $signed(32'h00000004);
 54    end
 55
 56    always @(b) begin: assig_process_cmp_3
 57        cmp_3 = b >= $signed(32'h00000004);
 58    end
 59
 60    always @(b) begin: assig_process_cmp_4
 61        cmp_4 = b != $signed(32'h00000004);
 62    end
 63
 64    always @(b) begin: assig_process_cmp_5
 65        cmp_5 = b == $signed(32'h00000004);
 66    end
 67
 68    always @(*) begin: assig_process_contOut
 69        contOut = const_private_signal;
 70    end
 71
 72    assign f = r;
 73    always @(negedge clk) begin: assig_process_fallingEdgeRam
 74        fallingEdgeRam[r_1] <= $signed(a[7:0]);
 75        k <= {24'h000000, $unsigned(fallingEdgeRam[r_1])};
 76    end
 77
 78    always @(a) begin: assig_process_fitted
 79        fitted = a[15:0];
 80    end
 81
 82    always @(a, b) begin: assig_process_g
 83        g = {{a[1] & $signed(b[1]), a[0] ^ $signed(b[0]) | a[1]}, a[5:0]};
 84    end
 85
 86    always @(a, r) begin: assig_process_h
 87        if (a[2])
 88            if (r)
 89                h = 8'h00;
 90            else if (a[1])
 91                h = 8'h01;
 92            else
 93                h = 8'h02;
 94    end
 95
 96    always @(posedge clk) begin: assig_process_j
 97        j <= rom[r_1];
 98    end
 99
100    assign out = 1'b0;
101    assign output_0 = 1'bx;
102    always @(posedge clk) begin: assig_process_r
103        if (~rst_n) begin
104            r_1 <= 2'b00;
105            r_0 <= 2'b00;
106            r <= 1'b0;
107        end else begin
108            r_1 <= r_next_1;
109            r_0 <= r_next_0;
110            r <= r_next;
111        end
112    end
113
114    assign r_next_0 = i;
115    assign r_next_1 = r_0;
116    always @(e, r) begin: assig_process_r_next_1
117        if (~r)
118            r_next = e;
119        else
120            r_next = r;
121    end
122
123    always @(a) begin: assig_process_sc_signal
124        case(a)
125            32'h00000001:
126                sc_signal = 8'h00;
127            32'h00000002:
128                sc_signal = 8'h01;
129            32'h00000003:
130                sc_signal = 8'h03;
131            default:
132                sc_signal = 8'h04;
133        endcase
134    end
135
136    initial begin
137        rom[0] = 8'h00;
138        rom[1] = 8'h01;
139        rom[2] = 8'h02;
140        rom[3] = 8'h03;
141    end
142
143endmodule
VHDL IEEE Std 1076-2002
  1LIBRARY IEEE;
  2USE IEEE.std_logic_1164.ALL;
  3USE IEEE.numeric_std.ALL;
  4--
  5--Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
  6--
  7--.. hwt-autodoc::
  8ENTITY Showcase0 IS
  9    PORT(
 10        a : IN UNSIGNED(31 DOWNTO 0);
 11        b : IN SIGNED(31 DOWNTO 0);
 12        c : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 13        clk : IN STD_LOGIC;
 14        cmp_0 : OUT STD_LOGIC;
 15        cmp_1 : OUT STD_LOGIC;
 16        cmp_2 : OUT STD_LOGIC;
 17        cmp_3 : OUT STD_LOGIC;
 18        cmp_4 : OUT STD_LOGIC;
 19        cmp_5 : OUT STD_LOGIC;
 20        contOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 21        d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 22        e : IN STD_LOGIC;
 23        f : OUT STD_LOGIC;
 24        fitted : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
 25        g : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 26        h : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 27        i : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
 28        j : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
 29        k : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 30        out_0 : OUT STD_LOGIC;
 31        output : OUT STD_LOGIC;
 32        rst_n : IN STD_LOGIC;
 33        sc_signal : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
 34    );
 35END ENTITY;
 36
 37ARCHITECTURE rtl OF Showcase0 IS
 38    TYPE arr_t_0 IS ARRAY (3 DOWNTO 0) OF SIGNED(7 DOWNTO 0);
 39    TYPE arr_t_1 IS ARRAY (3 DOWNTO 0) OF UNSIGNED(7 DOWNTO 0);
 40    CONSTANT const_private_signal : UNSIGNED(31 DOWNTO 0) := UNSIGNED'(X"0000007B");
 41    SIGNAL fallingEdgeRam : arr_t_0;
 42    SIGNAL r : STD_LOGIC := '0';
 43    SIGNAL r_0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
 44    SIGNAL r_1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
 45    SIGNAL r_next : STD_LOGIC;
 46    SIGNAL r_next_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
 47    SIGNAL r_next_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
 48    CONSTANT rom : arr_t_1 := (
 49        UNSIGNED'(X"00"),
 50        UNSIGNED'(X"01"),
 51        UNSIGNED'(X"02"),
 52        UNSIGNED'(X"03"));
 53BEGIN
 54    assig_process_c: PROCESS(a, b)
 55        VARIABLE tmpCastExpr_0 : UNSIGNED(31 DOWNTO 0);
 56    BEGIN
 57        tmpCastExpr_0 := a + UNSIGNED(b);
 58        c <= STD_LOGIC_VECTOR(tmpCastExpr_0);
 59    END PROCESS;
 60    cmp_0 <= '1' WHEN (a < UNSIGNED'(X"00000004")) ELSE '0';
 61    cmp_1 <= '1' WHEN (a > UNSIGNED'(X"00000004")) ELSE '0';
 62    cmp_2 <= '1' WHEN (b <= SIGNED'(X"00000004")) ELSE '0';
 63    cmp_3 <= '1' WHEN (b >= SIGNED'(X"00000004")) ELSE '0';
 64    cmp_4 <= '1' WHEN (b /= SIGNED'(X"00000004")) ELSE '0';
 65    cmp_5 <= '1' WHEN (b = SIGNED'(X"00000004")) ELSE '0';
 66    contOut <= STD_LOGIC_VECTOR(const_private_signal);
 67    f <= r;
 68    assig_process_fallingEdgeRam: PROCESS(clk)
 69        VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
 70        VARIABLE tmpCastExpr_2 : SIGNED(7 DOWNTO 0);
 71        VARIABLE tmpCastExpr_1 : UNSIGNED(31 DOWNTO 0);
 72    BEGIN
 73        tmpCastExpr_0 := RESIZE(a, 8);
 74        tmpCastExpr_2 := fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1)));
 75        tmpCastExpr_1 := RESIZE(UNSIGNED(tmpCastExpr_2), 32);
 76        IF FALLING_EDGE(clk) THEN
 77            fallingEdgeRam(TO_INTEGER(UNSIGNED(r_1))) <= SIGNED(tmpCastExpr_0);
 78            k <= STD_LOGIC_VECTOR(tmpCastExpr_1);
 79        END IF;
 80    END PROCESS;
 81    assig_process_fitted: PROCESS(a)
 82        VARIABLE tmpCastExpr_0 : UNSIGNED(15 DOWNTO 0);
 83    BEGIN
 84        tmpCastExpr_0 := RESIZE(a, 16);
 85        fitted <= STD_LOGIC_VECTOR(tmpCastExpr_0);
 86    END PROCESS;
 87    assig_process_g: PROCESS(a, b)
 88        VARIABLE tmpCastExpr_0 : UNSIGNED(5 DOWNTO 0);
 89    BEGIN
 90        tmpCastExpr_0 := RESIZE(a, 6);
 91        g <= (a(1) AND b(1)) & ((a(0) XOR b(0)) OR a(1)) & STD_LOGIC_VECTOR(tmpCastExpr_0);
 92    END PROCESS;
 93    assig_process_h: PROCESS(a, r)
 94    BEGIN
 95        IF a(2) = '1' THEN
 96            IF r = '1' THEN
 97                h <= X"00";
 98            ELSIF a(1) = '1' THEN
 99                h <= X"01";
100            ELSE
101                h <= X"02";
102            END IF;
103        END IF;
104    END PROCESS;
105    assig_process_j: PROCESS(clk)
106        VARIABLE tmpCastExpr_0 : UNSIGNED(7 DOWNTO 0);
107    BEGIN
108        tmpCastExpr_0 := rom(TO_INTEGER(UNSIGNED(r_1)));
109        IF RISING_EDGE(clk) THEN
110            j <= STD_LOGIC_VECTOR(tmpCastExpr_0);
111        END IF;
112    END PROCESS;
113    out_0 <= '0';
114    output <= 'X';
115    assig_process_r: PROCESS(clk)
116    BEGIN
117        IF RISING_EDGE(clk) THEN
118            IF rst_n = '0' THEN
119                r_1 <= "00";
120                r_0 <= "00";
121                r <= '0';
122            ELSE
123                r_1 <= r_next_1;
124                r_0 <= r_next_0;
125                r <= r_next;
126            END IF;
127        END IF;
128    END PROCESS;
129    r_next_0 <= i;
130    r_next_1 <= r_0;
131    assig_process_r_next_1: PROCESS(e, r)
132    BEGIN
133        IF r = '0' THEN
134            r_next <= e;
135        ELSE
136            r_next <= r;
137        END IF;
138    END PROCESS;
139    assig_process_sc_signal: PROCESS(a)
140    BEGIN
141        CASE a IS
142            WHEN UNSIGNED'(X"00000001") =>
143                sc_signal <= X"00";
144            WHEN UNSIGNED'(X"00000002") =>
145                sc_signal <= X"01";
146            WHEN UNSIGNED'(X"00000003") =>
147                sc_signal <= X"03";
148            WHEN OTHERS =>
149                sc_signal <= X"04";
150        END CASE;
151    END PROCESS;
152END ARCHITECTURE;
SystemC IEEE Std 1666-2011
  1#include <systemc.h>
  2
  3//
  4//Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
  5//
  6//.. hwt-autodoc::
  7SC_MODULE(Showcase0) {
  8    // ports
  9    sc_in<sc_uint<32>> a;
 10    sc_in<sc_int<32>> b;
 11    sc_out<sc_uint<32>> c;
 12    sc_in_clk clk;
 13    sc_out<sc_uint<1>> cmp_0;
 14    sc_out<sc_uint<1>> cmp_1;
 15    sc_out<sc_uint<1>> cmp_2;
 16    sc_out<sc_uint<1>> cmp_3;
 17    sc_out<sc_uint<1>> cmp_4;
 18    sc_out<sc_uint<1>> cmp_5;
 19    sc_out<sc_uint<32>> contOut;
 20    sc_in<sc_uint<32>> d;
 21    sc_in<sc_uint<1>> e;
 22    sc_out<sc_uint<1>> f;
 23    sc_out<sc_uint<16>> fitted;
 24    sc_out<sc_uint<8>> g;
 25    sc_out<sc_uint<8>> h;
 26    sc_in<sc_uint<2>> i;
 27    sc_out<sc_uint<8>> j;
 28    sc_out<sc_uint<32>> k;
 29    sc_out<sc_uint<1>> out;
 30    sc_out<sc_uint<1>> output;
 31    sc_in<sc_uint<1>> rst_n;
 32    sc_out<sc_uint<8>> sc_signal_0;
 33    // component instances
 34    // internal signals
 35    sc_uint<32> const_private_signal = sc_uint<32>("0x0000007B");
 36    sc_int<8> fallingEdgeRam[4];
 37    sc_uint<1> r = sc_uint<1>("0b0");
 38    sc_uint<2> r_0 = sc_uint<2>("0b00");
 39    sc_uint<2> r_1 = sc_uint<2>("0b00");
 40    sc_signal<sc_uint<1>> r_next;
 41    sc_signal<sc_uint<2>> r_next_0;
 42    sc_signal<sc_uint<2>> r_next_1;
 43    sc_uint<8> rom[4] = {sc_uint<8>("0x00"), 
 44        sc_uint<8>("0x01"), 
 45        sc_uint<8>("0x02"), 
 46        sc_uint<8>("0x03"), 
 47        };
 48    void assig_process_c() {
 49        c.write(static_cast<sc_uint<32>>(a.read() + static_cast<sc_uint<32>>(b.read())));
 50    }
 51
 52    void assig_process_cmp_0() {
 53        cmp_0.write(a.read() < sc_uint<32>("0x00000004"));
 54    }
 55
 56    void assig_process_cmp_1() {
 57        cmp_1.write(a.read() > sc_uint<32>("0x00000004"));
 58    }
 59
 60    void assig_process_cmp_2() {
 61        cmp_2.write(b.read() <= sc_int<32>("0x00000004"));
 62    }
 63
 64    void assig_process_cmp_3() {
 65        cmp_3.write(b.read() >= sc_int<32>("0x00000004"));
 66    }
 67
 68    void assig_process_cmp_4() {
 69        cmp_4.write(b.read() != sc_int<32>("0x00000004"));
 70    }
 71
 72    void assig_process_cmp_5() {
 73        cmp_5.write(b.read() == sc_int<32>("0x00000004"));
 74    }
 75
 76    void assig_process_contOut() {
 77        contOut.write(static_cast<sc_uint<32>>(const_private_signal));
 78    }
 79
 80    void assig_process_f() {
 81        f.write(r);
 82    }
 83
 84    void assig_process_fallingEdgeRam() {
 85        (fallingEdgeRam[r_1]).write(static_cast<sc_int<8>>(static_cast<sc_uint<8>>(a.read())));
 86        k = static_cast<sc_uint<32>>(static_cast<sc_uint<32>>(static_cast<sc_uint<8>>(fallingEdgeRam[r_1])));
 87    }
 88
 89    void assig_process_fitted() {
 90        fitted.write(static_cast<sc_uint<16>>(static_cast<sc_uint<16>>(a.read())));
 91    }
 92
 93    void assig_process_g() {
 94        sc_signal<sc_uint<2>> tmpConcat_1;
 95        sc_signal<sc_uint<8>> tmpConcat_0;
 96        tmpConcat_1.write((a.read()[sc_int<32>("0x00000001")] & static_cast<sc_uint<1>>(b.read()[sc_int<32>("0x00000001")]), a.read()[sc_int<32>("0x00000000")] ^ static_cast<sc_uint<1>>(b.read()[sc_int<32>("0x00000000")]) | a.read()[sc_int<32>("0x00000001")], ));
 97        tmpConcat_0.write((tmpConcat_1.read(), static_cast<sc_uint<6>>(static_cast<sc_uint<6>>(a.read())), ));
 98        g.write(tmpConcat_0.read());
 99    }
100
101    void assig_process_h() {
102        if (a.read()[sc_int<32>("0x00000002")])
103            if (r)
104                h.write(sc_uint<8>("0x00"));
105            else if (a.read()[sc_int<32>("0x00000001")])
106                h.write(sc_uint<8>("0x01"));
107            else
108                h.write(sc_uint<8>("0x02"));
109    }
110
111    void assig_process_j() {
112        j = static_cast<sc_uint<8>>(rom[r_1]);
113    }
114
115    void assig_process_out() {
116        out.write(sc_uint<1>("0b0"));
117    }
118
119    void assig_process_output() {
120        output.write(sc_uint<1>("0bX"));
121    }
122
123    void assig_process_r() {
124        if (~rst_n.read()) {
125            r_1 = sc_uint<2>("0b00");
126            r_0 = sc_uint<2>("0b00");
127            r = sc_uint<1>("0b0");
128        } else {
129            r_1 = r_next_1.read();
130            r_0 = r_next_0.read();
131            r = r_next.read();
132        }
133    }
134
135    void assig_process_r_next() {
136        r_next_0.write(i.read());
137    }
138
139    void assig_process_r_next_0() {
140        r_next_1.write(r_0);
141    }
142
143    void assig_process_r_next_1() {
144        if (~r)
145            r_next.write(e.read());
146        else
147            r_next.write(r);
148    }
149
150    void assig_process_sc_signal_0() {
151        switch(a.read()) {
152        case sc_uint<32>("0x00000001"): {
153                sc_signal_0.write(sc_uint<8>("0x00"));
154                break;
155            }
156        case sc_uint<32>("0x00000002"): {
157                sc_signal_0.write(sc_uint<8>("0x01"));
158                break;
159            }
160        case sc_uint<32>("0x00000003"): {
161                sc_signal_0.write(sc_uint<8>("0x03"));
162                break;
163            }
164        default:
165                sc_signal_0.write(sc_uint<8>("0x04"));
166        }
167    }
168
169    SC_CTOR(Showcase0) {
170        SC_METHOD(assig_process_c);
171        sensitive << a << b;
172        SC_METHOD(assig_process_cmp_0);
173        sensitive << a;
174        SC_METHOD(assig_process_cmp_1);
175        sensitive << a;
176        SC_METHOD(assig_process_cmp_2);
177        sensitive << b;
178        SC_METHOD(assig_process_cmp_3);
179        sensitive << b;
180        SC_METHOD(assig_process_cmp_4);
181        sensitive << b;
182        SC_METHOD(assig_process_cmp_5);
183        sensitive << b;
184        assig_process_contOut();
185        SC_METHOD(assig_process_f);
186        sensitive << r;
187        SC_METHOD(assig_process_fallingEdgeRam);
188        sensitive << clk.neg();
189        SC_METHOD(assig_process_fitted);
190        sensitive << a;
191        SC_METHOD(assig_process_g);
192        sensitive << a << b;
193        SC_METHOD(assig_process_h);
194        sensitive << a << r;
195        SC_METHOD(assig_process_j);
196        sensitive << clk.pos();
197        assig_process_out();
198        assig_process_output();
199        SC_METHOD(assig_process_r);
200        sensitive << clk.pos();
201        SC_METHOD(assig_process_r_next);
202        sensitive << i;
203        SC_METHOD(assig_process_r_next_0);
204        sensitive << r_0;
205        SC_METHOD(assig_process_r_next_1);
206        sensitive << e << r;
207        SC_METHOD(assig_process_sc_signal_0);
208        sensitive << a;
209        // connect ports
210    }
211};
HWT hwt.hwModule.HwModule class definition
  1from hwt.code import If, Switch, Concat
  2from hwt.code_utils import rename_signal
  3from hwt.hwIOs.std import HwIOSignal
  4from hwt.hwModule import HwModule
  5from hwt.hwParam import HwParam
  6from hwt.hdl.types.array import HArray
  7from hwt.hdl.types.bits import HBits
  8from hwt.hdl.types.defs import INT, SLICE, STR, BIT, FLOAT64
  9from hwt.hdl.types.enum import HEnum
 10
 11class Showcase0(HwModule):
 12    """
 13    Every HW component class has to be derived from :class:`hwt.hwModule.HwModule` class
 14    
 15    .. hwt-autodoc::
 16    
 17    """
 18    def hwDeclr(self):
 19        # ports
 20        self.a = HwIOSignal(HBits(32, signed=False))
 21        self.b = HwIOSignal(HBits(32, signed=True))
 22        self.c = HwIOSignal(HBits(32))._m()
 23        self.clk = HwIOSignal(HBits(1))
 24        self.cmp_0 = HwIOSignal(HBits(1))._m()
 25        self.cmp_1 = HwIOSignal(HBits(1))._m()
 26        self.cmp_2 = HwIOSignal(HBits(1))._m()
 27        self.cmp_3 = HwIOSignal(HBits(1))._m()
 28        self.cmp_4 = HwIOSignal(HBits(1))._m()
 29        self.cmp_5 = HwIOSignal(HBits(1))._m()
 30        self.contOut = HwIOSignal(HBits(32))._m()
 31        self.d = HwIOSignal(HBits(32))
 32        self.e = HwIOSignal(HBits(1))
 33        self.f = HwIOSignal(HBits(1))._m()
 34        self.fitted = HwIOSignal(HBits(16))._m()
 35        self.g = HwIOSignal(HBits(8))._m()
 36        self.h = HwIOSignal(HBits(8))._m()
 37        self.i = HwIOSignal(HBits(2))
 38        self.j = HwIOSignal(HBits(8))._m()
 39        self.k = HwIOSignal(HBits(32))._m()
 40        self.out = HwIOSignal(HBits(1))._m()
 41        self.output = HwIOSignal(HBits(1))._m()
 42        self.rst_n = HwIOSignal(HBits(1, negated=True))
 43        self.sc_signal = HwIOSignal(HBits(8))._m()
 44        # component instances
 45
 46    def hwImpl(self):
 47        a, b, c, clk, cmp_0, cmp_1, cmp_2, cmp_3, cmp_4, cmp_5, contOut, \
 48        d, e, f, fitted, g, h, i, j, k, out, \
 49        output, rst_n, sc_signal = \
 50        self.a, self.b, self.c, self.clk, self.cmp_0, self.cmp_1, self.cmp_2, self.cmp_3, self.cmp_4, self.cmp_5, self.contOut, \
 51        self.d, self.e, self.f, self.fitted, self.g, self.h, self.i, self.j, self.k, self.out, \
 52        self.output, self.rst_n, self.sc_signal
 53        # internal signals
 54        const_private_signal = HBits(32, signed=False).from_py(123)
 55        fallingEdgeRam = self._sig("fallingEdgeRam", HBits(8, signed=True)[4], def_val=None)
 56        r = self._sig("r", HBits(1), def_val=0)
 57        r_0 = self._sig("r_0", HBits(2), def_val=0)
 58        r_1 = self._sig("r_1", HBits(2), def_val=0)
 59        r_next = self._sig("r_next", HBits(1), def_val=None)
 60        r_next_0 = self._sig("r_next_0", HBits(2), def_val=None)
 61        r_next_1 = self._sig("r_next_1", HBits(2), def_val=None)
 62        rom = HBits(8, signed=False)[4].from_py({0: 0,
 63            1: 1,
 64            2: 2,
 65            3: 3
 66        })
 67        # assig_process_c
 68        c((a + b._explicit_cast(HBits(32, signed=False)))._explicit_cast(HBits(32)))
 69        # assig_process_cmp_0
 70        cmp_0(a < 4)
 71        # assig_process_cmp_1
 72        cmp_1(a > 4)
 73        # assig_process_cmp_2
 74        cmp_2(b <= 4)
 75        # assig_process_cmp_3
 76        cmp_3(b >= 4)
 77        # assig_process_cmp_4
 78        cmp_4(b != 4)
 79        # assig_process_cmp_5
 80        cmp_5(b._eq(4))
 81        # assig_process_contOut
 82        contOut(const_private_signal._explicit_cast(HBits(32)))
 83        # assig_process_f
 84        f(r)
 85        # assig_process_fallingEdgeRam
 86        If(clk._onFallingEdge(),
 87            fallingEdgeRam[r_1](a._trunc(8)._explicit_cast(HBits(8, signed=True))),
 88            k(fallingEdgeRam[r_1]._explicit_cast(HBits(8, signed=False))._zext(32)._explicit_cast(HBits(32)))
 89        )
 90        # assig_process_fitted
 91        fitted(a._trunc(16)._explicit_cast(HBits(16)))
 92        # assig_process_g
 93        g(Concat(Concat(a[1] & b[1], a[0] ^ b[0] | a[1]), a._trunc(6)._explicit_cast(HBits(6))))
 94        # assig_process_h
 95        If(a[2],
 96            If(r,
 97                h(0)
 98            ).Elif(a[1],
 99                h(1)
100            ).Else(
101                h(2)
102            )
103        )
104        # assig_process_j
105        If(clk._onRisingEdge(),
106            j(rom[r_1]._explicit_cast(HBits(8)))
107        )
108        # assig_process_out
109        out(0)
110        # assig_process_output
111        output(None)
112        # assig_process_r
113        If(clk._onRisingEdge(),
114            If(~rst_n._explicit_cast(HBits(1)),
115                r_1(0),
116                r_0(0),
117                r(0)
118            ).Else(
119                r_1(r_next_1),
120                r_0(r_next_0),
121                r(r_next)
122            )
123        )
124        # assig_process_r_next
125        r_next_0(i)
126        # assig_process_r_next_0
127        r_next_1(r_0)
128        # assig_process_r_next_1
129        If(~r,
130            r_next(e)
131        ).Else(
132            r_next(r)
133        )
134        # assig_process_sc_signal
135        Switch(a)\
136            .Case(1,
137                sc_signal(0))\
138            .Case(2,
139                sc_signal(1))\
140            .Case(3,
141                sc_signal(3))\
142            .Default(
143                sc_signal(4))
class hwtLib.examples.showcase0.Showcase0[source]

Bases: HwModule

Every HW component class has to be derived from hwt.hwModule.HwModule class

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits, unsigned> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits, signed> - SLAVE

  • c - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

  • fitted - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - MASTER

  • contOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

  • d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - SLAVE

  • e - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • f - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • g - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • cmp - of type hwt.hwIOs.hwIOArray.HwIOArray - MASTER

  • h - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • i - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

  • j - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • output - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • sc_signal - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • k - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

schematic
__annotations__ = {}
__init__()[source]
hwDeclr()[source]

In this function collecting of public interfaces is performed on every attribute assignment. Instances of Interface or hwt.hwModule.HwModule are recognized by hwt.hwModule.HwModule instance and are used as public interface of this unit.

Master interfaces are marked by “._m()”, meaning of master direction is specified in HwIO class. For simple signal master direction means output.

hwImpl()[source]

Purpose of this method In this method all public interfaces and configuration has been made and they can not be edited.

hwtLib.examples.showcase0.foo(condition0, statements, condition1, fallback0, fallback1)[source]

Python functions used as macro

hwtLib.examples.showcase0_hwt module

class hwtLib.examples.showcase0_hwt.Showcase0(hdlName: str | None = None)[source]

Bases: HwModule

Every HW component class has to be derived from hwt.hwModule.HwModule class

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits, unsigned> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits, signed> - SLAVE

  • c - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

  • clk - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • cmp_0 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cmp_1 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cmp_2 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cmp_3 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cmp_4 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cmp_5 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • contOut - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

  • d - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - SLAVE

  • e - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • f - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • fitted - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 16bits> - MASTER

  • g - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • h - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • i - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 2bits> - SLAVE

  • j - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

  • k - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 32bits> - MASTER

  • out - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • output - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • rst_n - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit, n> - SLAVE

  • sc_signal - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

schematic
__annotations__ = {}

hwtLib.examples.simpleHwModule module

class hwtLib.examples.simpleHwModule.SimpleHwModule(hdlName: str | None = None)[source]

Bases: HwModule

In order to create a new unit you have to make new class derived from HwModule.

You can use sphinx-hwt plugin for sphinx document generator to generate interactive schematic and documentation. Schematic is generated by directive bellow.

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
hwDeclr()[source]

hwDeclr() is like header of HwModule. There you have to declare things which should be visible from outside.

hwImpl()[source]

hwImpl() is like body of unit. Logic and connections are specified i`qn this function.

hwtLib.examples.simpleHwModule2withNonDirectIntConnection module

class hwtLib.examples.simpleHwModule2withNonDirectIntConnection.Simple2withNonDirectIntConnectionTC(methodName='runTest')[source]

Bases: SimTestCase

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_passData()[source]
class hwtLib.examples.simpleHwModule2withNonDirectIntConnection.SimpleHwModule2withNonDirectIntConnection(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

HDL IO:
schematic
__annotations__ = {}

hwtLib.examples.simpleHwModuleAxi4Stream module

class hwtLib.examples.simpleHwModuleAxi4Stream.SimpleHwModuleAxi4Stream(hdlName: str | None = None)[source]

Bases: HwModule

Example of unit with axi stream interface

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

HDL IO:
schematic
__annotations__ = {}

hwtLib.examples.simpleHwModuleWithHwParam module

class hwtLib.examples.simpleHwModuleWithHwParam.SimpleHwModuleWithHwParam(hdlName: str | None = None)[source]

Bases: HwModule

Simple parametrized module.

HDL params:

  • DATA_WIDTH - default value 8 of type int

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - MASTER

schematic
__annotations__ = {}
class hwtLib.examples.simpleHwModuleWithHwParam.SimpleHwModuleWithParamTC(methodName='runTest')[source]

Bases: SimTestCase

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_simple()[source]

hwtLib.examples.simpleHwModuleWithNonDirectIntConncetion module

class hwtLib.examples.simpleHwModuleWithNonDirectIntConncetion.SimpleHwModuleWithNonDirectIntConncetion(hdlName: str | None = None)[source]

Bases: HwModule

Example of fact that interfaces does not have to be only extern the can be used even for connection inside unit

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • c - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
class hwtLib.examples.simpleHwModuleWithNonDirectIntConncetion.SimpleModuleWithNonDirectIntConncetionTC(methodName='runTest')[source]

Bases: SimTestCase

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_passData()[source]

hwtLib.examples.simple_ip module

hwtLib.examples.timers module

class hwtLib.examples.timers.DynamicCounterInstancesExample(hdlName: str | None = None)[source]

Bases: HwModule

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • period - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 10bits> - SLAVE

  • en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • rstCntr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • cntr0 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • cntr1 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
class hwtLib.examples.timers.TimerInfoTest(hdlName: str | None = None)[source]

Bases: HwModule

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • tick1 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick2 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick16 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick17 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick34 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick256 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • tick384 - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
class hwtLib.examples.timers.TimerTC(methodName='runTest')[source]

Bases: SimTestCase

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
tearDown()[source]

Hook method for deconstructing the test fixture after testing it.

test_basic()[source]
test_dynamic_simple()[source]
class hwtLib.examples.timers.TimerTestHwModule(hdlName: str | None = None)[source]

Bases: HwModule

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

  • tick1 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick2 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick16 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick17 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick34 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick256 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

  • tick384 - of type hwt.hwIOs.std.HwIORdVldSync - MASTER

HDL components:
schematic
__annotations__ = {}