hwtLib.examples.axi package

Various examples with an AMBA AXI invterfaces

Subpackages

• hwtLib.examples.axi.oooOp package
  • Submodules
  • hwtLib.examples.axi.oooOp.counterArray module
  • hwtLib.examples.axi.oooOp.counterHashTable module
  • hwtLib.examples.axi.oooOp.testUtils module

Submodules

hwtLib.examples.axi.debugbusmonitor module

class hwtLib.examples.axi.debugbusmonitor.DebugBusMonitorExampleAxi(hdl_name_override: Optional[str] = None)

Bases: Unit

An example how to use hwtLib.abstract.debug_bus_monitor.DebugBusMonitor

HDL params

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• s - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

• din0 - of type hwt.interfaces.std.Handshaked - SLAVE

• dout0 - of type hwt.interfaces.std.Handshaked - MASTER

• din1 - of type hwt.interfaces.std.Handshaked - SLAVE

• dout1 - of type hwt.interfaces.std.Handshaked - MASTER

• other_clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• other_rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• din2 - of type hwt.interfaces.std.Handshaked - SLAVE

• dout2 - of type hwt.interfaces.std.Handshaked - MASTER

HDL components

• reg - of type hwtLib.handshaked.reg.HandshakedReg

• db - of type hwtLib.abstract.debug_bus_monitor.DebugBusMonitor

• cdc_dataIn - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_dataIn_snapshot - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_dataOut - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_dataOut_snapshot - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_din2 - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_din2_snapshot - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_dout2 - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

• cdc_dout2_snapshot - of type hwtLib.abstract.monitorIntf.MonitorIntfVldSyncedCdc

schematic

hwtLib.examples.axi.simpleAxiRegs module

class hwtLib.examples.axi.simpleAxiRegs.SimpleAxiRegs(hdl_name_override: Optional[str] = None)

Bases: Unit

Axi litle mapped registers example, 0x0 - reg0 0x4 - reg1

HDL params

• ADDR_WIDTH - default value 8 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• axi - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

HDL components

• conv - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic