hwtLib.examples.axi package

Various examples with an AMBA AXI invterfaces

Subpackages

• hwtLib.examples.axi.oooOp package
  • Submodules
  • hwtLib.examples.axi.oooOp.counterArray module
    • OooOpExampleCounterArray
      • OooOpExampleCounterArray.__annotations__
      • OooOpExampleCounterArray.main_op()
  • hwtLib.examples.axi.oooOp.counterHashTable module
    • OooOpExampleCounterHashTable
      • OooOpExampleCounterHashTable.OPERATION
        • OooOpExampleCounterHashTable.OPERATION.LOOKUP
        • OooOpExampleCounterHashTable.OPERATION.LOOKUP_OR_SWAP
        • OooOpExampleCounterHashTable.OPERATION.SWAP
      • OooOpExampleCounterHashTable.__annotations__
      • OooOpExampleCounterHashTable.do_swap_original_and_current_state()
      • OooOpExampleCounterHashTable.get_latest_key_match()
      • OooOpExampleCounterHashTable.key_compare()
      • OooOpExampleCounterHashTable.main_op()
      • OooOpExampleCounterHashTable.main_op_on_lookup_match_update()
      • OooOpExampleCounterHashTable.propagate_trans_st()
      • OooOpExampleCounterHashTable.write_cancel()
    • _example_OooOpExampleCounterHashTable()
  • hwtLib.examples.axi.oooOp.testUtils module
    • OutOfOrderCummulativeOp_dump_pipeline()
    • OutOfOrderCummulativeOp_dump_pipeline_html()

Submodules

hwtLib.examples.axi.debugbusmonitor module

class hwtLib.examples.axi.debugbusmonitor.DebugBusMonitorExampleAxi(hdlName: str | None = None)

Bases: HwModule

An example how to use hwtLib.abstract.debug_bus_monitor.DebugBusMonitor

HDL params:

• ADDR_WIDTH - default value 32 of type int

• DATA_WIDTH - default value 64 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• s - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

• din0 - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dout0 - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

• din1 - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dout1 - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

• other_clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• other_rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• din2 - of type hwt.hwIOs.std.HwIODataRdVld - SLAVE

• dout2 - of type hwt.hwIOs.std.HwIODataRdVld - MASTER

HDL components:

• reg - of type hwtLib.handshaked.reg.HandshakedReg

• db - of type hwtLib.abstract.debug_bus_monitor.DebugBusMonitor

• cdc_dataIn - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_dataIn_snapshot - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_dataOut - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_dataOut_snapshot - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_din2 - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_din2_snapshot - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_dout2 - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

• cdc_dout2_snapshot - of type hwtLib.abstract.hwIOMonitor.HwIOMonitorDataVldCdc

schematic

__annotations__ = {}

hwtLib.examples.axi.simpleAxiRegs module

class hwtLib.examples.axi.simpleAxiRegs.SimpleAxiRegs(hdlName: str | None = None)

Bases: HwModule

Axi litle mapped registers example, 0x0 - reg0 0x4 - reg1

HDL params:

• ADDR_WIDTH - default value 8 of type int

• DATA_WIDTH - default value 32 of type int

HDL IO:

• clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

• rst_n - of type hwt.hwIOs.std.HwIORst_n with dtype=<HBits, 1bit, n> - SLAVE

• axi - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

HDL components:

• conv - of type hwtLib.amba.axiLite_comp.endpoint.AxiLiteEndpoint

schematic

__annotations__ = {}