hwtLib.examples.axi.oooOp package

Submodules

hwtLib.examples.axi.oooOp.counterArray module

class hwtLib.examples.axi.oooOp.counterArray.OooOpExampleCounterArray(hdl_name_override: Optional[str] = None)[source]

Bases: OutOfOrderCummulativeOp

This components uses array of counters accessible through axi interface. These counters are incremented using “dataIn” interface in a coherent way. The operation may finish out of order but the data on “dataOut” and in the memory will be correct.

HDL params

  • MAIN_STATE_T - default value <Bits, 32bits, unsigned> of type hwt.hdl.types.bits.Bits

  • TRANSACTION_STATE_T - default value None of type None

  • PIPELINE_CONFIG - default value OutOfOrderCummulativeOpPipelineConfig(READ_DATA_RECEIVE=0, STATE_LOAD=2, WRITE_BACK=3, WAIT_FOR_WRITE_ACK=4, WRITE_HISTORY_SIZE=1) of type hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpPipelineConfig

  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO
HDL components
schematic
main_op(dst_main_state: OOOOpPipelineStage, src_main_state: OOOOpPipelineStage)[source]

Interpretation of main operatorion of the pipeline.

hwtLib.examples.axi.oooOp.counterHashTable module

class hwtLib.examples.axi.oooOp.counterHashTable.OooOpExampleCounterHashTable(hdl_name_override: Optional[str] = None)[source]

Bases: OutOfOrderCummulativeOp

This components mantains the hash table where value is a counter. This hash table is accesed throught the axi interface. These counters are incremented using “dataIn” interface in a coherent way. The operation may finish out of order but the data on “dataOut” and in the memory will be correct. The same applies for the swap operations (all operations).

HDL params

  • MAIN_STATE_T - default value struct { <Bits, 1bit> item_valid <Bits, 256bits> key <Bits, 32bits> value <Bits, 223bits> padding } of type hwt.hdl.types.struct.HStruct

  • TRANSACTION_STATE_T - default value struct { <Bits, 1bit> reset struct { <Bits, 1bit> item_valid <Bits, 256bits> key <Bits, 32bits> value <Bits, 223bits> padding } original_data <Bits, 1bit> key_match <Bits, 2bits> operation } of type hwt.hdl.types.struct.HStruct

  • PIPELINE_CONFIG - default value OutOfOrderCummulativeOpPipelineConfig(READ_DATA_RECEIVE=0, STATE_LOAD=2, WRITE_BACK=3, WAIT_FOR_WRITE_ACK=4, WRITE_HISTORY_SIZE=1) of type hwtLib.amba.axi_comp.oooOp.utils.OutOfOrderCummulativeOpPipelineConfig

  • ADDR_WIDTH - default value 19 of type int

  • DATA_WIDTH - default value 512 of type int

  • ID_WIDTH - default value 6 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

HDL IO
HDL components
schematic
class OPERATION[source]

Bases: object

LOOKUP = 2
LOOKUP_OR_SWAP = 1
SWAP = 0
do_swap_original_and_current_state(src_st: OOOOpPipelineStage, dst_st: OOOOpPipelineStage)[source]
Returns

a signal which is a flag which is 1 if the data in transactional state and the data from/to memory should be swapped

get_latest_key_match(st: OOOOpPipelineStage)[source]
Returns

a signal which is flag which signalizes that in this clock cycle the st has the key which match with latest colliding item or with transactional data of this state

key_compare(st0: OOOOpPipelineStage, st1: OOOOpPipelineStage)[source]
main_op(dst_st: OOOOpPipelineStage, src_st: OOOOpPipelineStage)[source]

A main opration of counter incrementation

Note

This function is called for write back state and its predecessor. However because of write bypass this function is called multiple times for each bypass as well.

main_op_on_lookup_match_update(dst_st: OOOOpPipelineStage, src_st: OOOOpPipelineStage)[source]
propagate_trans_st(src_st: OOOOpPipelineStage, dst_st: OOOOpPipelineStage)[source]

Pass the state of operation (lookup/swap) in pipeline in state before write_back chech if the key matches and

Note

The trasaction can potentially collide with anything back in pipeline The pipeline supports flushing that implies that each data word has individual condition for moving to the next stage.

write_cancel(write_back_st: OOOOpPipelineStage)[source]
Returns

signal which if it is 1 the transaction state update is not writen back to memory (e.g. 1 if key does not match and we do not want to update counters)

hwtLib.examples.axi.oooOp.counterHashTable._example_OooOpExampleCounterHashTable()[source]

hwtLib.examples.axi.oooOp.testUtils module

hwtLib.examples.axi.oooOp.testUtils.OutOfOrderCummulativeOp_dump_pipeline(tc: SimTestCase, u: OooOpExampleCounterHashTable, model: BasicRtlSimModel, states: list)[source]
hwtLib.examples.axi.oooOp.testUtils.OutOfOrderCummulativeOp_dump_pipeline_html(file: StringIO, u: OooOpExampleCounterHashTable, states: list)[source]