hwtLib.examples.hierarchy package

Submodules

hwtLib.examples.hierarchy.extractHierarchy module

class hwtLib.examples.hierarchy.extractHierarchy.ExtractedUnit(externInputs: UniqList[RtlSignal], externObjsToExtract: UniqList[Union[RtlSignal, Operator]], externOutputs: UniqList[RtlSignal], hdl_name_override: Optional[str] = None)

Bases: Unit

An unit which will extract selected circuit from parent on instantiation.

__init__(externInputs: UniqList[RtlSignal], externObjsToExtract: UniqList[Union[RtlSignal, Operator]], externOutputs: UniqList[RtlSignal], hdl_name_override: Optional[str] = None)

_handleUpdateForOutput(o: RtlSignal, translation: Dict[RtlSignal, RtlSignal], interOuts: Dict[RtlSignal, RtlSignal], outerIoMap: Dict[RtlSignal, RtlSignal], toTranslate: Deque[Union[Operator, HdlStatement, HdlPortItem]])

_moveOrCopyCircuitFromParent(translation: Dict[RtlSignal, RtlSignal], interOuts: Dict[RtlSignal, RtlSignal], outerIoMap: Dict[RtlSignal, RtlSignal])

_signalsForSubUnitEntity(context: RtlNetlist, prefix: str)

generate signals in this context for all ports of this subunit

hwtLib.examples.hierarchy.extractHierarchy.consumeExpr(e: Union[RtlSignal, HValue], inputs: UniqList[RtlSignal], seenObjs: UniqList[Union[RtlSignal, Operator]])

To make output code readable we must extract also expressions used in statements if they are private to selected statements.

Note

Walk from endpoint to a driver. For every signal on path if all its endpoints are in seenObjs, add this to seenObjs and continue search on its drivers.

hwtLib.examples.hierarchy.extractHierarchy.extractNetlistPartToSubunit(inputs: UniqList[RtlSignal], outputs: UniqList[RtlSignal], priv: UniqList[Union[RtlSignal, Operator]]) → ExtractedUnit

Attention

extraction is executed on unit instantiation

Attention

each object in priv must be reachable from inputs

hwtLib.examples.hierarchy.extractHierarchy.extractRegsToSubunit(regs: Sequence[RtlSyncSignal]) → ExtractedUnit

hwtLib.examples.hierarchy.extractHierarchyExamples module

class hwtLib.examples.hierarchy.extractHierarchyExamples.UnitWidthDynamicallyGeneratedSubunitsForManyRegisters(hdl_name_override: Optional[str] = None)

Bases: Unit

class hwtLib.examples.hierarchy.extractHierarchyExamples.UnitWidthDynamicallyGeneratedSubunitsForRegisters(hdl_name_override: Optional[str] = None)

Bases: Unit

class hwtLib.examples.hierarchy.extractHierarchyExamples.UnitWidthDynamicallyGeneratedSubunitsForRegistersWithExpr(hdl_name_override: Optional[str] = None)

Bases: Unit

hwtLib.examples.hierarchy.groupOfBlockrams module

class hwtLib.examples.hierarchy.groupOfBlockrams.GroupOfBlockrams(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• ADDR_WIDTH - default value 8 of type int

• DATA_WIDTH - default value 64 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• en - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• we - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• addr - of type hwt.interfaces.std.Signal with dtype=<Bits, 8bits> - SLAVE

• in_w_a - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE

• in_w_b - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE

• in_r_a - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE

• in_r_b - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - SLAVE

• out_w_a - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER

• out_w_b - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER

• out_r_a - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER

• out_r_b - of type hwt.interfaces.std.Signal with dtype=<Bits, 64bits> - MASTER

HDL components

• bramR - of type hwtLib.mem.ram.RamMultiClock

• bramW - of type hwtLib.mem.ram.RamMultiClock

schematic

hwtLib.examples.hierarchy.netFilter module

class hwtLib.examples.hierarchy.netFilter.Exporter(hdl_name_override: Optional[str] = None)

Bases: EmptyUnit

class hwtLib.examples.hierarchy.netFilter.Filter(hdl_name_override: Optional[str] = None)

Bases: EmptyUnit

class hwtLib.examples.hierarchy.netFilter.HeadFieldExtractor(hdl_name_override: Optional[str] = None)

Bases: EmptyUnit

class hwtLib.examples.hierarchy.netFilter.NetFilter(hdl_name_override: Optional[str] = None)

Bases: Unit

This unit has actually no functionality it is just example of hierarchical design.

HDL params

• DATA_WIDTH - default value 64 of type int

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• din - of type hwtLib.amba.axis.AxiStream - SLAVE

• export - of type hwtLib.amba.axis.AxiStream - MASTER

• cfg - of type hwtLib.amba.axi4Lite.Axi4Lite - SLAVE

HDL components

• hfe - of type hwtLib.examples.hierarchy.netFilter.HeadFieldExtractor

• patternMatch - of type hwtLib.examples.hierarchy.netFilter.PatternMatch

• filter - of type hwtLib.examples.hierarchy.netFilter.Filter

• exporter - of type hwtLib.examples.hierarchy.netFilter.Exporter

• gen_dout_splitCopy_0 - of type hwtLib.amba.axis_comp.splitCopy.AxiSSplitCopy

schematic

class hwtLib.examples.hierarchy.netFilter.PatternMatch(hdl_name_override: Optional[str] = None)

Bases: EmptyUnit

hwtLib.examples.hierarchy.rippleadder module

class hwtLib.examples.hierarchy.rippleadder.FullAdder(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL IO

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• ci - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• s - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

• co - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

schematic

class hwtLib.examples.hierarchy.rippleadder.RippleAdder0(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• p_wordlength - default value 4 of type int

HDL IO

• ci - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• s - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

• co - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

• fa0 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa1 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa2 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa3 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

schematic

class hwtLib.examples.hierarchy.rippleadder.RippleAdder1(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• p_wordlength - default value 4 of type int

HDL IO

• ci - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• s - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

• co - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

• fa_0 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_1 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_2 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_3 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

schematic

class hwtLib.examples.hierarchy.rippleadder.RippleAdder2(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• p_wordlength - default value 4 of type int

HDL IO

• ci - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• s - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

• co - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

• fa_0 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_1 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_2 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_3 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

schematic

class hwtLib.examples.hierarchy.rippleadder.RippleAdder3(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• p_wordlength - default value 4 of type int

HDL IO

• ci - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - SLAVE

• s - of type hwt.interfaces.std.Signal with dtype=<Bits, 4bits> - MASTER

• co - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

• fa_0 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_1 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_2 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

• fa_3 - of type hwtLib.examples.hierarchy.rippleadder.FullAdder

schematic

hwtLib.examples.hierarchy.simpleSubunit module

class hwtLib.examples.hierarchy.simpleSubunit.SimpleSubunit(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL IO

• a - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - SLAVE

• b - of type hwt.interfaces.std.Signal with dtype=<Bits, 1bit> - MASTER

HDL components

• subunit0 - of type hwtLib.examples.simple.SimpleUnit

schematic

hwtLib.examples.hierarchy.simpleSubunit2 module

class hwtLib.examples.hierarchy.simpleSubunit2.SimpleSubunit2(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• USE_STRB - default value True of type bool

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• a0 - of type hwtLib.amba.axis.AxiStream - SLAVE

• b0 - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• subunit0 - of type hwtLib.examples.simpleAxiStream.SimpleUnitAxiStream

schematic

class hwtLib.examples.hierarchy.simpleSubunit2.SimpleSubunit2TC(methodName='runTest')

Bases: SimTestCase

classmethod setUpClass()

Hook method for setting up class fixture before running tests in the class.

test_simplePass()

hwtLib.examples.hierarchy.simpleSubunit3 module

class hwtLib.examples.hierarchy.simpleSubunit3.SimpleSubunit3(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• DATA_WIDTH - default value 128 of type int

• USE_STRB - default value True of type bool

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• a0 - of type hwtLib.amba.axis.AxiStream - SLAVE

• b0 - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• subunit0 - of type hwtLib.examples.simpleAxiStream.SimpleUnitAxiStream

schematic

class hwtLib.examples.hierarchy.simpleSubunit3.SimpleSubunit3TC(methodName='runTest')

Bases: SimpleSubunit2TC

classmethod setUpClass()

Hook method for setting up class fixture before running tests in the class.

hwtLib.examples.hierarchy.unitToUnitConnection module

class hwtLib.examples.hierarchy.unitToUnitConnection.UnitToUnitConnection(hdl_name_override: Optional[str] = None)

Bases: Unit

HDL params

• DATA_WIDTH - default value 8 of type int

• USE_STRB - default value True of type bool

HDL IO

• clk - of type hwt.interfaces.std.Clk with dtype=<Bits, 1bit> - SLAVE

• rst_n - of type hwt.interfaces.std.Rst_n with dtype=<Bits, 1bit> - SLAVE

• a0 - of type hwtLib.amba.axis.AxiStream - SLAVE

• b0 - of type hwtLib.amba.axis.AxiStream - MASTER

HDL components

• u0 - of type hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnection

• u1 - of type hwtLib.examples.simple2withNonDirectIntConnection.Simple2withNonDirectIntConnection

schematic

class hwtLib.examples.hierarchy.unitToUnitConnection.UnitToUnitConnectionTC(methodName='runTest')

Bases: SimpleSubunit2TC

classmethod setUpClass()

Hook method for setting up class fixture before running tests in the class.

hwtLib.examples.hierarchy.unitWrapper module

class hwtLib.examples.hierarchy.unitWrapper.UnitWrapper(baseUnit: Unit)

Bases: Unit

Class which creates wrapper around original unit instance, original unit will be stored inside as subunit named baseUnit

Note

This is example of lazy loaded interfaces and generating of external interfaces based on internal structure.

__init__(baseUnit: Unit)

Parameters

baseUnit – An hwt.synthesizer.unit.Unit instance which should be hidden in this wrapper.

_connectBaseUnitToThisWrap(origToWrapInfMap)

_copyParamsAndInterfaces()

_getDefaultName()

_get_hdl_doc()