hwtLib.examples.hierarchy package

Submodules

hwtLib.examples.hierarchy.extractHierarchy module

class hwtLib.examples.hierarchy.extractHierarchy.ExtractedHwModule(externInputs: SetList[RtlSignal], externObjsToExtract: SetList[RtlSignal | HOperatorNode], externOutputs: SetList[RtlSignal], hdlName: str | None = None)[source]

Bases: HwModule

An unit which will extract selected circuit from parent on instantiation.

__annotations__ = {}
__init__(externInputs: SetList[RtlSignal], externObjsToExtract: SetList[RtlSignal | HOperatorNode], externOutputs: SetList[RtlSignal], hdlName: str | None = None)[source]
_handleUpdateForOutput(o: RtlSignal, translation: Dict[RtlSignal, RtlSignal], interOuts: Dict[RtlSignal, RtlSignal], outerIoMap: Dict[RtlSignal, RtlSignal], toTranslate: Deque[HOperatorNode | HdlStatement | HdlPortItem])[source]
_moveOrCopyCircuitFromParent(translation: Dict[RtlSignal, RtlSignal], interOuts: Dict[RtlSignal, RtlSignal], outerIoMap: Dict[RtlSignal, RtlSignal])[source]
_signalsForSubHwModuleEntity(context: RtlNetlist, prefix: str)[source]

generate signals in this context for all ports of this subunit

hwtLib.examples.hierarchy.extractHierarchy.consumeExpr(e: RtlSignal | HConst, inputs: SetList[RtlSignal], seenObjs: SetList[RtlSignal | HOperatorNode])[source]

To make output code readable we must extract also expressions used in statements if they are private to selected statements.

Note:

Walk from endpoint to a driver. For every signal on path if all its endpoints are in seenObjs, add this to seenObjs and continue search on its drivers.

hwtLib.examples.hierarchy.extractHierarchy.extractNetlistPartToSubmodule(inputs: SetList[RtlSignal], outputs: SetList[RtlSignal], priv: SetList[RtlSignal | HOperatorNode]) → ExtractedHwModule[source]
Attention:

extraction is executed on unit instantiation

Attention:

each object in priv must be reachable from inputs

hwtLib.examples.hierarchy.extractHierarchy.extractRegsToSubmodule(regs: Sequence[RtlSignal]) → ExtractedHwModule[source]

hwtLib.examples.hierarchy.extractHierarchyExamples module

class hwtLib.examples.hierarchy.extractHierarchyExamples.HwModuleWidthDynamicallyGeneratedSubunitsForManyRegisters(hdlName: str | None = None)[source]

Bases: HwModule

__annotations__ = {}
class hwtLib.examples.hierarchy.extractHierarchyExamples.HwModuleWidthDynamicallyGeneratedSubunitsForRegisters(hdlName: str | None = None)[source]

Bases: HwModule

__annotations__ = {}
class hwtLib.examples.hierarchy.extractHierarchyExamples.HwModuleWidthDynamicallyGeneratedSubunitsForRegistersWithExpr(hdlName: str | None = None)[source]

Bases: HwModule

__annotations__ = {}

hwtLib.examples.hierarchy.groupOfBlockrams module

class hwtLib.examples.hierarchy.groupOfBlockrams.GroupOfBlockrams(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • ADDR_WIDTH - default value 8 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO:

  • clk - of type hwt.hwIOs.std.HwIOClk with dtype=<HBits, 1bit> - SLAVE

  • en - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • we - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • addr - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 8bits> - SLAVE

  • in_w_a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - SLAVE

  • in_w_b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - SLAVE

  • in_r_a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - SLAVE

  • in_r_b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - SLAVE

  • out_w_a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - MASTER

  • out_w_b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - MASTER

  • out_r_a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - MASTER

  • out_r_b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 64bits> - MASTER

HDL components:
schematic
__annotations__ = {}

hwtLib.examples.hierarchy.hwModuleToHwModuleConnection module

class hwtLib.examples.hierarchy.hwModuleToHwModuleConnection.HwModuleToHwModuleConnection(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • DATA_WIDTH - default value 8 of type int

  • USE_STRB - default value True of type bool

HDL IO:
HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.hwModuleToHwModuleConnection.HwModuleToHwModuleConnectionTC(methodName='runTest')[source]

Bases: SimpleSubModule2TC

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

hwtLib.examples.hierarchy.hwModuleWrapper module

class hwtLib.examples.hierarchy.hwModuleWrapper.HwModuleWrapper(baseModule: HwModule)[source]

Bases: HwModule

Class which creates wrapper around original unit instance, original unit will be stored inside as subunit named baseModule

Note:

This is example of lazy loaded interfaces and generating of external interfaces based on internal structure.

__annotations__ = {}
__init__(baseModule: HwModule)[source]
Parameters:

baseModule – An hwt.hwModule.HwModule instance which should be hidden in this wrapper.

_connectBaseModuleToThisWrap(origToWrapHwIOMap)[source]
_copyParamsAndInterfaces()[source]
_getDefaultName()[source]
_get_hdl_doc()[source]

hwtLib.examples.hierarchy.netFilter module

class hwtLib.examples.hierarchy.netFilter.Exporter(hdlName: str | None = None)[source]

Bases: EmptyHwModule

__annotations__ = {}
class hwtLib.examples.hierarchy.netFilter.Filter(hdlName: str | None = None)[source]

Bases: EmptyHwModule

__annotations__ = {}
class hwtLib.examples.hierarchy.netFilter.HeadFieldExtractor(hdlName: str | None = None)[source]

Bases: EmptyHwModule

__annotations__ = {}
class hwtLib.examples.hierarchy.netFilter.NetFilter(hdlName: str | None = None)[source]

Bases: HwModule

This unit has actually no functionality it is just example of hierarchical design.

HDL params:

  • DATA_WIDTH - default value 64 of type int

HDL IO:
HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.netFilter.PatternMatch(hdlName: str | None = None)[source]

Bases: EmptyHwModule

__annotations__ = {}

hwtLib.examples.hierarchy.rippleadder module

class hwtLib.examples.hierarchy.rippleadder.FullAdder(hdlName: str | None = None)[source]

Bases: HwModule

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • ci - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • s - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

  • co - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.rippleadder.RippleAdder0(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • p_wordlength - default value 4 of type int

HDL IO:

  • ci - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • s - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

  • co - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.rippleadder.RippleAdder1(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • p_wordlength - default value 4 of type int

HDL IO:

  • ci - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • s - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

  • co - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.rippleadder.RippleAdder2(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • p_wordlength - default value 4 of type int

HDL IO:

  • ci - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • s - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

  • co - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.rippleadder.RippleAdder3(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • p_wordlength - default value 4 of type int

HDL IO:

  • ci - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - SLAVE

  • s - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 4bits> - MASTER

  • co - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:
schematic
__annotations__ = {}

hwtLib.examples.hierarchy.simpleSubHwModule1 module

class hwtLib.examples.hierarchy.simpleSubHwModule1.SimpleSubHwModule1(hdlName: str | None = None)[source]

Bases: HwModule

HDL IO:

  • a - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - SLAVE

  • b - of type hwt.hwIOs.std.HwIOSignal with dtype=<HBits, 1bit> - MASTER

HDL components:
schematic
__annotations__ = {}

hwtLib.examples.hierarchy.simpleSubHwModule2 module

class hwtLib.examples.hierarchy.simpleSubHwModule2.SimpleSubHwModule2(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • USE_STRB - default value True of type bool

HDL IO:
HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.simpleSubHwModule2.SimpleSubModule2TC(methodName='runTest')[source]

Bases: SimTestCase

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.

test_simplePass()[source]

hwtLib.examples.hierarchy.simpleSubHwModule3 module

class hwtLib.examples.hierarchy.simpleSubHwModule3.SimpleSubHwModule3(hdlName: str | None = None)[source]

Bases: HwModule

HDL params:

  • DATA_WIDTH - default value 128 of type int

  • USE_STRB - default value True of type bool

HDL IO:
HDL components:
schematic
__annotations__ = {}
class hwtLib.examples.hierarchy.simpleSubHwModule3.SimpleSubModule3TC(methodName='runTest')[source]

Bases: SimpleSubModule2TC

__annotations__ = {}
_classSetupFailed = False
_class_cleanups = []
classmethod setUpClass()[source]

Hook method for setting up class fixture before running tests in the class.