hwtLib.amba.axi_comp.lsu package

This package is dedicated to AXI Load/Store Units (LSU) a others like.

Other LSU implementations:

Submodules

hwtLib.amba.axi_comp.lsu.fifo_oooread module

class hwtLib.amba.axi_comp.lsu.fifo_oooread.FifoOutOfOrderRead(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Container of FIFO pointers and flags where the items can be discarded in out of order manner.

_images/FifoOutOfOrderRead.png

Item state control scheme:

  • write_confirm: the item is now allocated in the fifo and ready to be read

  • read_execute: the item is locked for updates and is currently being read

  • read_confirm: the item is entirely readed and it is ready to be deallocated

HDL params
  • ITEMS - default value 4 of type int

  • KEY_WIDTH - default value 0 of type int

HDL IO
schematic
class hwtLib.amba.axi_comp.lsu.fifo_oooread.FifoOutOfOrderReadFiltered(hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.amba.axi_comp.lsu.fifo_oooread.FifoOutOfOrderRead

FifoOutOfOrderRead with an additional cam to filter transactions by same key :attention: this component does not contains the item storage, it is just container of such a FIFO logic

_images/FifoOutOfOrderReadFiltered.png

Item state control scheme:

  • write_execute: preallocate the item for writing (and add key to CAM for filtering)

  • write_confirm: the item is now allocated in the fifo and ready to be read

  • read_execute: the item is locked for updates and is currently being read

  • read_confirm: the item is entirely readed and it is ready to be deallocated

HDL params
  • ITEMS - default value 4 of type int

  • KEY_WIDTH - default value 8 of type int

  • HAS_READ_LOOKUP - default value False of type bool

HDL IO
HDL components
schematic

hwtLib.amba.axi_comp.lsu.interfaces module

class hwtLib.amba.axi_comp.lsu.interfaces.AddrDataIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO
class hwtLib.amba.axi_comp.lsu.interfaces.AxiWriteAggregatorReadIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

An interface which is used to speculatively read data from AxiWriteAggregator

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

HDL IO
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwtLib.amba.axi_comp.lsu.interfaces.AxiWriteAggregatorWriteIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.Handshaked

An interface which is used to push write data to a AxiWriteAggregator

HDL params
  • DATA_WIDTH - default value 64 of type int

  • ADDR_WIDTH - default value 32 of type int

HDL IO
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwtLib.amba.axi_comp.lsu.interfaces.AxiWriteAggregatorWriteIntfAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf: Handshaked, allowNoReset=False)[source]

Bases: hwt.interfaces.agents.handshaked.HandshakedAgent

get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

class hwtLib.amba.axi_comp.lsu.interfaces.AxiWriteAggregatorWriteTmpIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwtLib.amba.axi_comp.lsu.interfaces.AxiWriteAggregatorWriteIntf

Interface for tmp input register on store buffer write input

HDL params
  • DATA_WIDTH - default value 64 of type int

  • ADDR_WIDTH - default value 32 of type int

  • ITEMS - default value 64 of type int

HDL IO
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

hwtLib.amba.axi_comp.lsu.read_aggregator module

class hwtLib.amba.axi_comp.lsu.read_aggregator.AxiReadAggregator(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

This is a component which reduces reads from same address.

This component has several slots for read transactions, Each slot has it’s own address record in CAM which is used to detect reads from same address, if the read is from same address which is currently being loaded. The read thread is put to sleep until data for previous read is received. After data is received it is copied as a response also for this transaction.

_images/AxiReadAggregator.png
HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 2 of type int

  • ADDR_USER_WIDTH - default value 0 of type int

  • CACHE_LINE_SIZE - default value 64 of type int

HDL IO
HDL components
schematic
add_addr_cam_out_reg(item_vld: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)[source]
read_data_section(read_ack: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, waiting_transaction_id: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, waiting_transaction_vld: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, data_copy_override: hwt.interfaces.std.VldSynced)[source]
read_request_section(read_ack: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, item_vld: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, waiting_transaction_id: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, waiting_transaction_vld: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, data_copy_override: hwt.interfaces.std.VldSynced)[source]
hwtLib.amba.axi_comp.lsu.read_aggregator._example_AxiReadAggregator()[source]

hwtLib.amba.axi_comp.lsu.store_queue_write_propagating module

class hwtLib.amba.axi_comp.lsu.store_queue_write_propagating.AxiStoreQueueWritePropagating(hdl_name_override: Optional[str] = None)[source]

Bases: hwtLib.amba.axi_comp.lsu.write_aggregator.AxiWriteAggregator

An extension of hwtLib.amba.axi_comp.lsu.write_aggregator.AxiWriteAggregator with an IO for a communication with an hwtLib.amba.axi_comp.lsu.load_queue.AxiLoadQueue Does the same thing and allows hwtLib.amba.axi_comp.lsu.load_queue_write_propagating.AxiLoadQueueWritePropagating to speculatively read the data and listen for write transactions. The component allows for write to bypass read, which makes it suitable for cumulative operations, but more complicated for a generic use.

Variables
  • speculative_read_addr – port used for load buffer to speculatively read the data from this component. If data is not present the speculative_read_data returns RESP_EXOKAY error. The data may also be flushed during the read this is marked with RESP_SLVERR error.

  • speculative_read_data – Read data for speculative read.

speculative_read_handler()[source]

Connect the speculative_read port to internal storages of the AxiWriteAggregator

We need to handle several cases:

  1. the data is currently in tmp register

  2. the data was in tmp register and now is in data memory

  3. the data is in data memory

  4. the data was in data memory and now it is deallocated

  5. the data was not found anywhere

Handling of speculative read has following stages:

  1. search input register and main address CAM for data

  2. optionaly load the data from ram

  3. send data to speculative_read_data and set resp to error if was not found it may also happen that the data was flushed in the mean time

_images/AxiStoreQueueWritePropagating_speculativeRead.png
Note

speculative read never block the write channel and thus data may be invalid if the speculative read data is stalled. This should be handled in master of speculative read port (Other component which is using this component).

class hwtLib.amba.axi_comp.lsu.store_queue_write_propagating.AxiWriteAggregatorWriteTmpIntf(masterDir=DIRECTION.OUT, hdl_name: Optional[Union[str, Dict[str, str]]] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.Handshaked

hwtLib.amba.axi_comp.lsu.write_aggregator module

class hwtLib.amba.axi_comp.lsu.write_aggregator.AxiWriteAggregator(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

A buffer which is used for write data from cache.

It manages:

  • out of order write acknowledge

  • write transaction merging

_images/AxiWriteAggregator.png
HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 32 of type int

  • ID_WIDTH - default value 2 of type inta parameter which specifies width of axi id signal, it also specifies the number of items in this buffer (2**ID_WIDTH)

  • CACHE_LINE_SIZE - default value 4 of type int

  • MAX_BLOCK_DATA_WIDTH - default value 8 of type intspecifies maximum data width of RAM (used to prevent synthesis problems for tools which can not handle too wide memories with byte enable)

HDL IO
HDL components
schematic
_declr_data_ram()[source]
data_insert(items: hwtLib.mem.ramCumulativeMask.BramPort_withReadMask_withoutClk)[source]
  • check if this address is already present in address CAM or w_in_reg

  • if it is possible to update data in w_in_reg or in data_ram of this buffer

  • else allocate new data (insert to address CAM of ooo_fifo) and store data to w_in_reg

  • if w_in_tmp reg is not beeing updated, forward it to the data_ram to flush it to main memory

_images/AxiWriteAggregator_data_insert.png
Note

we must not let data from tmp reg if next w_in has same address (we have to update tmp reg instead)

hwtLib.amba.axi_comp.lsu.write_aggregator._example_AxiWriteAggregator()[source]

hwtLib.amba.axi_comp.lsu.write_aggregator_write_dispatcher module

class hwtLib.amba.axi_comp.lsu.write_aggregator_write_dispatcher.AxiWriteAggregatorWriteDispatcher(hdl_name_override: Optional[str] = None)[source]

Bases: hwt.synthesizer.unit.Unit

Use hwtLib.amba.axi_comp.lsu.fifo_oooread.FifoOutOfOrderReadFiltered read ports to query an AXI transaction info and copy paste this transaction from BRAM to AXI.

HDL params
  • ADDR_WIDTH - default value 32 of type int

  • DATA_WIDTH - default value 64 of type int

  • ID_WIDTH - default value 6 of type int

  • CACHE_LINE_SIZE - default value 64 of type int

HDL IO
schematic
data_ram_read_to_bus_w(items: hwtLib.mem.ramCumulativeMask.BramPort_withReadMask_withoutClk, item_last: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, w_out: hwtLib.amba.axi4.Axi4_w)[source]

Read write data from data_ram

Parameters

item_last – the signal with last flag for data (notes a last beat in burst) sampled in the same time as an read address

dispatch_addr(id_to_use: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, addr: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, a: hwtLib.amba.axi4.Axi4_addr)[source]
  • if there is a valid item in buffer dispatch read request

dispatch_data(aw_ld: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, pop_ptr: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, pop_req: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, pop_wait: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, items: hwtLib.mem.ramCumulativeMask.BramPort_withReadMask_withoutClk, aw_out_ready: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, w_out: hwtLib.amba.axi4.Axi4_w)[source]
  • if there is a valid item in buffer dispatch write request and write data

  • handshaked FIFO read logic

precompute_constants()[source]
receive_write_confirm(b: hwtLib.amba.axi4.Axi4_b, read_confirm: hwt.interfaces.std.Handshaked)[source]